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[Qemu-devel] [PATCH 46/52] target-m68k: introduce byte and word cc_ops
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From: |
Laurent Vivier |
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Subject: |
[Qemu-devel] [PATCH 46/52] target-m68k: introduce byte and word cc_ops |
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Date: |
Wed, 4 May 2016 23:21:03 +0200 |
Signed-off-by: Laurent Vivier <address@hidden>
---
target-m68k/cpu.h | 6 +--
target-m68k/helper.c | 25 +++++++++----
target-m68k/translate.c | 99 ++++++++++++++++++++++++++++++-------------------
3 files changed, 80 insertions(+), 50 deletions(-)
diff --git a/target-m68k/cpu.h b/target-m68k/cpu.h
index 5ce77e4..1112502 100644
--- a/target-m68k/cpu.h
+++ b/target-m68k/cpu.h
@@ -147,11 +147,11 @@ typedef enum {
CC_OP_FLAGS,
/* X in cc_x, C = X, N in cc_n, Z in cc_n, V via cc_n/cc_v. */
- CC_OP_ADD,
- CC_OP_SUB,
+ CC_OP_ADDB, CC_OP_ADDW, CC_OP_ADDL,
+ CC_OP_SUBB, CC_OP_SUBW, CC_OP_SUBL,
/* X in cc_x, {N,Z,C,V} via cc_n/cc_v. */
- CC_OP_CMP,
+ CC_OP_CMPB, CC_OP_CMPW, CC_OP_CMPL,
/* X in cc_x, C = 0, V = 0, N in cc_n, Z in cc_n. */
CC_OP_LOGIC,
diff --git a/target-m68k/helper.c b/target-m68k/helper.c
index 76dda44..4d346a7 100644
--- a/target-m68k/helper.c
+++ b/target-m68k/helper.c
@@ -544,32 +544,41 @@ void HELPER(mac_set_flags)(CPUM68KState *env, uint32_t
acc)
}
}
+#define EXTSIGN(val, index) ( \
+ (index == 0) ? (int8_t)(val) : ((index == 1) ? (int16_t)(val) : (val)) \
+)
#define COMPUTE_CCR(op, x, n, z, v, c) { \
switch (op) { \
case CC_OP_FLAGS: \
/* Everything in place. */ \
break; \
- case CC_OP_ADD: \
+ case CC_OP_ADDB: \
+ case CC_OP_ADDW: \
+ case CC_OP_ADDL: \
res = n; \
src2 = v; \
- src1 = res - src2; \
+ src1 = EXTSIGN(res - src2, op - CC_OP_ADDB); \
c = x; \
z = n; \
v = (res ^ src1) & ~(src1 ^ src2); \
break; \
- case CC_OP_SUB: \
+ case CC_OP_SUBB: \
+ case CC_OP_SUBW: \
+ case CC_OP_SUBL: \
res = n; \
src2 = v; \
- src1 = res + src2; \
+ src1 = EXTSIGN(res + src2, op - CC_OP_SUBB); \
c = x; \
z = n; \
v = (res ^ src1) & (src1 ^ src2); \
break; \
- case CC_OP_CMP: \
+ case CC_OP_CMPB: \
+ case CC_OP_CMPW: \
+ case CC_OP_CMPL: \
src1 = n; \
src2 = v; \
- res = src1 - src2; \
+ res = EXTSIGN(src1 - src2, op - CC_OP_CMPB); \
n = res; \
z = res; \
c = src1 < src2; \
@@ -590,16 +599,16 @@ uint32_t cpu_m68k_get_ccr(CPUM68KState *env)
uint32_t res, src1, src2;
x = env->cc_x;
- c = env->cc_c;
n = env->cc_n;
z = env->cc_z;
v = env->cc_v;
+ c = env->cc_c;
COMPUTE_CCR(env->cc_op, x, n, z, v, c);
n = n >> 31;
- v = v >> 31;
z = (z == 0);
+ v = v >> 31;
return x*CCF_X + n*CCF_N + z*CCF_Z + v*CCF_V + c*CCF_C;
}
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index a8e9b64..2b6ba15 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -176,9 +176,9 @@ typedef void (*disas_proc)(CPUM68KState *env, DisasContext
*s, uint16_t insn);
static const uint8_t cc_op_live[CC_OP_NB] = {
[CC_OP_FLAGS] = CCF_C | CCF_V | CCF_Z | CCF_N | CCF_X,
- [CC_OP_ADD] = CCF_X | CCF_N | CCF_V,
- [CC_OP_SUB] = CCF_X | CCF_N | CCF_V,
- [CC_OP_CMP] = CCF_X | CCF_N | CCF_V,
+ [CC_OP_ADDB ... CC_OP_ADDL] = CCF_X | CCF_N | CCF_V,
+ [CC_OP_SUBB ... CC_OP_SUBL] = CCF_X | CCF_N | CCF_V,
+ [CC_OP_CMPB ... CC_OP_CMPL] = CCF_X | CCF_N | CCF_V,
[CC_OP_LOGIC] = CCF_X | CCF_N
};
@@ -452,6 +452,33 @@ static TCGv gen_lea_indexed(CPUM68KState *env,
DisasContext *s, TCGv base)
return add;
}
+/* Sign or zero extend a value. */
+
+static inline void gen_ext(TCGv res, TCGv val, int opsize, int sign)
+{
+ switch (opsize) {
+ case OS_BYTE:
+ if (sign) {
+ tcg_gen_ext8s_i32(res, val);
+ } else {
+ tcg_gen_ext8u_i32(res, val);
+ }
+ break;
+ case OS_WORD:
+ if (sign) {
+ tcg_gen_ext16s_i32(res, val);
+ } else {
+ tcg_gen_ext16u_i32(res, val);
+ }
+ break;
+ case OS_LONG:
+ tcg_gen_mov_i32(res, val);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
/* Evaluate all the CC flags. */
static void gen_flush_flags(DisasContext *s)
@@ -462,13 +489,16 @@ static void gen_flush_flags(DisasContext *s)
case CC_OP_FLAGS:
return;
- case CC_OP_ADD:
+ case CC_OP_ADDB:
+ case CC_OP_ADDW:
+ case CC_OP_ADDL:
tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X);
tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
/* Compute signed overflow for addition. */
t0 = tcg_temp_new();
t1 = tcg_temp_new();
tcg_gen_sub_i32(t0, QREG_CC_N, QREG_CC_V);
+ gen_ext(t0, t0, s->cc_op - CC_OP_ADDB, 1);
tcg_gen_xor_i32(t1, QREG_CC_N, QREG_CC_V);
tcg_gen_xor_i32(QREG_CC_V, QREG_CC_V, t0);
tcg_temp_free(t0);
@@ -476,13 +506,16 @@ static void gen_flush_flags(DisasContext *s)
tcg_temp_free(t1);
break;
- case CC_OP_SUB:
+ case CC_OP_SUBB:
+ case CC_OP_SUBW:
+ case CC_OP_SUBL:
tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X);
tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
/* Compute signed overflow for subtraction. */
t0 = tcg_temp_new();
t1 = tcg_temp_new();
tcg_gen_add_i32(t0, QREG_CC_N, QREG_CC_V);
+ gen_ext(t0, t0, s->cc_op - CC_OP_SUBB, 1);
tcg_gen_xor_i32(t1, QREG_CC_N, QREG_CC_V);
tcg_gen_xor_i32(QREG_CC_V, QREG_CC_V, t0);
tcg_temp_free(t0);
@@ -490,9 +523,12 @@ static void gen_flush_flags(DisasContext *s)
tcg_temp_free(t1);
break;
- case CC_OP_CMP:
+ case CC_OP_CMPB:
+ case CC_OP_CMPW:
+ case CC_OP_CMPL:
tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_C, QREG_CC_N, QREG_CC_V);
tcg_gen_sub_i32(QREG_CC_Z, QREG_CC_N, QREG_CC_V);
+ gen_ext(QREG_CC_Z, QREG_CC_Z, s->cc_op - CC_OP_CMPB, 1);
/* Compute signed overflow for subtraction. */
t0 = tcg_temp_new();
tcg_gen_xor_i32(t0, QREG_CC_Z, QREG_CC_N);
@@ -524,33 +560,6 @@ static void gen_flush_flags(DisasContext *s)
s->cc_op_synced = 1;
}
-/* Sign or zero extend a value. */
-
-static inline void gen_ext(TCGv res, TCGv val, int opsize, int sign)
-{
- switch (opsize) {
- case OS_BYTE:
- if (sign) {
- tcg_gen_ext8s_i32(res, val);
- } else {
- tcg_gen_ext8u_i32(res, val);
- }
- break;
- case OS_WORD:
- if (sign) {
- tcg_gen_ext16s_i32(res, val);
- } else {
- tcg_gen_ext16u_i32(res, val);
- }
- break;
- case OS_LONG:
- tcg_gen_mov_i32(res, val);
- break;
- default:
- g_assert_not_reached();
- }
-}
-
static inline TCGv gen_extend(TCGv val, int opsize, int sign)
{
TCGv tmp;
@@ -571,10 +580,17 @@ static void gen_logic_cc(DisasContext *s, TCGv val, int
opsize)
set_cc_op(s, CC_OP_LOGIC);
}
-static void gen_update_cc_add(TCGv dest, TCGv src)
+static void gen_update_cc_cmp(DisasContext *s, TCGv dest, TCGv src, int opsize)
{
tcg_gen_mov_i32(QREG_CC_N, dest);
tcg_gen_mov_i32(QREG_CC_V, src);
+ set_cc_op(s, CC_OP_CMPB + opsize);
+}
+
+static void gen_update_cc_add(TCGv dest, TCGv src, int opsize)
+{
+ gen_ext(QREG_CC_N, dest, opsize, 1);
+ tcg_gen_mov_i32(QREG_CC_V, src);
}
static inline int opsize_bytes(int opsize)
@@ -819,7 +835,7 @@ static void gen_cc_cond(DisasCompare *c, DisasContext *s,
int cond)
CCOp op = s->cc_op;
/* The CC_OP_CMP form can handle most normal comparisons directly. */
- if (op == CC_OP_CMP) {
+ if (op == CC_OP_CMPB || op == CC_OP_CMPW || op == CC_OP_CMPL) {
c->g1 = c->g2 = 1;
c->v1 = QREG_CC_N;
c->v2 = QREG_CC_V;
@@ -842,6 +858,7 @@ static void gen_cc_cond(DisasCompare *c, DisasContext *s,
int cond)
c->v2 = tcg_const_i32(0);
c->v1 = tmp = tcg_temp_new();
tcg_gen_sub_i32(tmp, QREG_CC_N, QREG_CC_V);
+ gen_ext(tmp, tmp, op - CC_OP_CMPB, 1);
/* fallthru */
case 12: /* GE */
case 13: /* LT */
@@ -864,7 +881,6 @@ static void gen_cc_cond(DisasCompare *c, DisasContext *s,
int cond)
c->v1 = c->v2;
tcond = TCG_COND_NEVER;
goto done;
- case 14: /* GT (!(Z || (N ^ V))) */
case 15: /* LE (Z || (N ^ V)) */
/* Logic operations clear V, which simplifies LE to (Z || N),
and since Z and N are co-located, this becomes a normal
@@ -885,7 +901,9 @@ static void gen_cc_cond(DisasCompare *c, DisasContext *s,
int cond)
case 10: /* PL (!N) */
case 11: /* MI (N) */
/* Several cases represent N normally. */
- if (op == CC_OP_ADD || op == CC_OP_SUB || op == CC_OP_LOGIC) {
+ if (op == CC_OP_ADDB || op == CC_OP_ADDW || op == CC_OP_ADDL ||
+ op == CC_OP_SUBB || op == CC_OP_SUBW || op == CC_OP_SUBL ||
+ op == CC_OP_LOGIC) {
c->v1 = QREG_CC_N;
tcond = TCG_COND_LT;
goto done;
@@ -894,7 +912,9 @@ static void gen_cc_cond(DisasCompare *c, DisasContext *s,
int cond)
case 6: /* NE (!Z) */
case 7: /* EQ (Z) */
/* Some cases fold Z into N. */
- if (op == CC_OP_ADD || op == CC_OP_SUB || op == CC_OP_LOGIC) {
+ if (op == CC_OP_ADDB || op == CC_OP_ADDW || op == CC_OP_ADDL ||
+ op == CC_OP_SUBB || op == CC_OP_SUBW || op == CC_OP_SUBL ||
+ op == CC_OP_LOGIC) {
tcond = TCG_COND_EQ;
c->v1 = QREG_CC_N;
goto done;
@@ -903,7 +923,8 @@ static void gen_cc_cond(DisasCompare *c, DisasContext *s,
int cond)
case 4: /* CC (!C) */
case 5: /* CS (C) */
/* Some cases fold C into X. */
- if (op == CC_OP_ADD || op == CC_OP_SUB) {
+ if (op == CC_OP_ADDB || op == CC_OP_ADDW || op == CC_OP_ADDL ||
+ op == CC_OP_ADDB || op == CC_OP_ADDW || op == CC_OP_ADDL) {
tcond = TCG_COND_NE;
c->v1 = QREG_CC_X;
goto done;
--
2.5.5
- Re: [Qemu-devel] [PATCH 33/52] target-m68k: inline divu/divs, (continued)
- [Qemu-devel] [PATCH 40/52] target-m68k: add exg ops, Laurent Vivier, 2016/05/04
- [Qemu-devel] [PATCH 41/52] target-m68k: add addressing modes to not, Laurent Vivier, 2016/05/04
- [Qemu-devel] [PATCH 44/52] target-m68k: and can manage word and byte operands, Laurent Vivier, 2016/05/04
- [Qemu-devel] [PATCH 42/52] target-m68k: eor can manage word and byte operands, Laurent Vivier, 2016/05/04
- [Qemu-devel] [PATCH 45/52] target-m68k: suba/adda can manage word operand, Laurent Vivier, 2016/05/04
- [Qemu-devel] [PATCH 46/52] target-m68k: introduce byte and word cc_ops,
Laurent Vivier <=
- [Qemu-devel] [PATCH 43/52] target-m68k: or can manage word and byte operands, Laurent Vivier, 2016/05/04
- [Qemu-devel] [PATCH 49/52] target-m68k: cmp manages word and bytes operands, Laurent Vivier, 2016/05/04
- [Qemu-devel] [PATCH 47/52] target-m68k: add addressing modes to neg, Laurent Vivier, 2016/05/04
- [Qemu-devel] [PATCH 48/52] target-m68k: add/sub manage word and byte operands, Laurent Vivier, 2016/05/04
- [Qemu-devel] [PATCH 51/52] target-m68k: add cmpm, Laurent Vivier, 2016/05/04