[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH v6 17/26] ioapic: keep RO bits for IOAPIC entry
From: |
Peter Xu |
Subject: |
[Qemu-devel] [PATCH v6 17/26] ioapic: keep RO bits for IOAPIC entry |
Date: |
Thu, 5 May 2016 11:25:52 +0800 |
Currently IOAPIC RO bits can be written. To be better aligned with
hardware, we should let them read-only.
Reviewed-by: Radim Krčmář <address@hidden>
Signed-off-by: Peter Xu <address@hidden>
---
hw/intc/ioapic.c | 4 ++++
include/hw/i386/ioapic_internal.h | 5 +++++
2 files changed, 9 insertions(+)
diff --git a/hw/intc/ioapic.c b/hw/intc/ioapic.c
index b41ab89..d7ebb5c 100644
--- a/hw/intc/ioapic.c
+++ b/hw/intc/ioapic.c
@@ -307,6 +307,7 @@ ioapic_mem_write(void *opaque, hwaddr addr, uint64_t val,
default:
index = (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1;
if (index >= 0 && index < IOAPIC_NUM_PINS) {
+ uint64_t ro_bits = s->ioredtbl[index] & IOAPIC_RO_BITS;
if (s->ioregsel & 1) {
s->ioredtbl[index] &= 0xffffffff;
s->ioredtbl[index] |= (uint64_t)val << 32;
@@ -314,6 +315,9 @@ ioapic_mem_write(void *opaque, hwaddr addr, uint64_t val,
s->ioredtbl[index] &= ~0xffffffffULL;
s->ioredtbl[index] |= val;
}
+ /* restore RO bits */
+ s->ioredtbl[index] &= IOAPIC_RW_BITS;
+ s->ioredtbl[index] |= ro_bits;
ioapic_service(s);
}
}
diff --git a/include/hw/i386/ioapic_internal.h
b/include/hw/i386/ioapic_internal.h
index d279f2d..31dafb3 100644
--- a/include/hw/i386/ioapic_internal.h
+++ b/include/hw/i386/ioapic_internal.h
@@ -48,6 +48,11 @@
#define IOAPIC_LVT_DEST_MODE (1 << IOAPIC_LVT_DEST_MODE_SHIFT)
#define IOAPIC_LVT_DELIV_MODE (7 << IOAPIC_LVT_DELIV_MODE_SHIFT)
+/* Bits that are read-only for IOAPIC entry */
+#define IOAPIC_RO_BITS (IOAPIC_LVT_REMOTE_IRR | \
+ IOAPIC_LVT_DELIV_STATUS)
+#define IOAPIC_RW_BITS (~(uint64_t)IOAPIC_RO_BITS)
+
#define IOAPIC_TRIGGER_EDGE 0
#define IOAPIC_TRIGGER_LEVEL 1
--
2.4.11
- Re: [Qemu-devel] [PATCH v6 08/26] intel_iommu: provide helper function vtd_get_iommu, (continued)
- [Qemu-devel] [PATCH v6 09/26] intel_iommu: add IR translation faults defines, Peter Xu, 2016/05/04
- [Qemu-devel] [PATCH v6 10/26] intel_iommu: Add support for PCI MSI remap, Peter Xu, 2016/05/04
- [Qemu-devel] [PATCH v6 11/26] q35: ioapic: add support for emulated IOAPIC IR, Peter Xu, 2016/05/04
- [Qemu-devel] [PATCH v6 12/26] ioapic: introduce ioapic_entry_parse() helper, Peter Xu, 2016/05/04
- [Qemu-devel] [PATCH v6 13/26] intel_iommu: add support for split irqchip, Peter Xu, 2016/05/04
- [Qemu-devel] [PATCH v6 14/26] q35: add "intremap" parameter to enable IR, Peter Xu, 2016/05/04
- [Qemu-devel] [PATCH v6 15/26] intel_iommu: introduce IEC notifiers, Peter Xu, 2016/05/04
- [Qemu-devel] [PATCH v6 16/26] ioapic: register VT-d IEC invalidate notifier, Peter Xu, 2016/05/04
- [Qemu-devel] [PATCH v6 17/26] ioapic: keep RO bits for IOAPIC entry,
Peter Xu <=
- [Qemu-devel] [PATCH v6 18/26] ioapic: clear remote irr bit for edge-triggered interrupts, Peter Xu, 2016/05/04
- [Qemu-devel] [PATCH v6 19/26] intel_iommu: Add support for Extended Interrupt Mode, Peter Xu, 2016/05/04
- [Qemu-devel] [PATCH v6 20/26] intel_iommu: add SID validation for IR, Peter Xu, 2016/05/04
- [Qemu-devel] [PATCH v6 21/26] x86-iommu: introduce parent class, Peter Xu, 2016/05/04
- [Qemu-devel] [PATCH v6 22/26] x86-iommu: replace existing VT-d hooks into X86 ones, Peter Xu, 2016/05/04
- [Qemu-devel] [PATCH v6 23/26] kvm-irqchip: simplify kvm_irqchip_add_msi_route, Peter Xu, 2016/05/04
- [Qemu-devel] [PATCH v6 25/26] kvm-irqchip: x86: add msi route notify fn, Peter Xu, 2016/05/04
- [Qemu-devel] [PATCH v6 26/26] kvm-irqchip: do explicit commit when update irq, Peter Xu, 2016/05/04