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Re: [Qemu-devel] [PATCH 10/23] hw/intc/arm_gicv3: Implement functions to
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH 10/23] hw/intc/arm_gicv3: Implement functions to identify next pending irq |
Date: |
Thu, 19 May 2016 14:21:31 +0100 |
On 19 May 2016 at 13:59, Shannon Zhao <address@hidden> wrote:
>
>
> On 2016/5/10 1:29, Peter Maydell wrote:
>> + uint32_t pend, grpmask;
>> + uint32_t pending = *gic_bmp_ptr32(s->pending, irq - GIC_INTERNAL);
>> + uint32_t edge_trigger = *gic_bmp_ptr32(s->edge_trigger, irq -
>> GIC_INTERNAL);
>> + uint32_t level = *gic_bmp_ptr32(s->level, irq - GIC_INTERNAL);
>> + uint32_t group = *gic_bmp_ptr32(s->group, irq - GIC_INTERNAL);
>> + uint32_t grpmod = *gic_bmp_ptr32(s->grpmod, irq - GIC_INTERNAL);
>> + uint32_t enable = *gic_bmp_ptr32(s->enabled, irq - GIC_INTERNAL);
>> +
> Since you use "irq - GIC_INTERNAL" many times, how about moving into the
> gic_bmp_ptr32()?
The bmp* functions are supposed to be generic (with APIs matching
the bitmap.h ones), so passing it X should give you bit X in the bitmap.
Maybe it would be less confusing to make the bitmaps all have 32 unused
bits at the start, so the bit for interrupt X is bit X in the bitmap...
That only costs us five words of memory per CPU, so it seems worth
it for the code clarity and avoiding annoying bugs.
>> /**
>> + * gicv3_irq_group:
>> + *
>> + * Return the group which this interrupt is configured as (GICV3_G0,
>> + * GICV3_G1 or GICV3_G1NS).
>> + */
>> +static inline int gicv3_irq_group(GICv3State *s, GICv3CPUState *cs, int irq)
> use uint32_t instead of int in this and other functions?
Neither interrupt numbers nor group numbers are particularly
large or specifically 32-bit, so 'int' seemed the most reasonable
type to use.
thanks
-- PMM
- [Qemu-devel] [PATCH 20/23] target-arm/monitor.c: Advertise emulated GICv3 in capabilities, (continued)
- [Qemu-devel] [PATCH 20/23] target-arm/monitor.c: Advertise emulated GICv3 in capabilities, Peter Maydell, 2016/05/09
- [Qemu-devel] [PATCH 16/23] hw/intc/arm_gicv3: Implement gicv3_cpuif_update(), Peter Maydell, 2016/05/09
- [Qemu-devel] [PATCH 19/23] target-arm/machine.c: Allow user to request GICv3 emulation, Peter Maydell, 2016/05/09
- [Qemu-devel] [PATCH 02/23] bitops.h: Implement half-shuffle and half-unshuffle ops, Peter Maydell, 2016/05/09
- [Qemu-devel] [PATCH 05/23] target-arm: Add mp-affinity property for ARM CPU class, Peter Maydell, 2016/05/09
- [Qemu-devel] [PATCH 04/23] target-arm: Provide hook to tell GICv3 about changes of security state, Peter Maydell, 2016/05/09
- [Qemu-devel] [PATCH 18/23] hw/intc/arm_gicv3: Add IRQ handling CPU interface registers, Peter Maydell, 2016/05/09
- [Qemu-devel] [PATCH 07/23] hw/intc/arm_gicv3: Move irq lines into GICv3CPUState structure, Peter Maydell, 2016/05/09
- [Qemu-devel] [PATCH 10/23] hw/intc/arm_gicv3: Implement functions to identify next pending irq, Peter Maydell, 2016/05/09
- [Qemu-devel] [PATCH 12/23] hw/intc/arm_gicv3: Implement GICv3 redistributor registers, Peter Maydell, 2016/05/09
- [Qemu-devel] [PATCH 15/23] hw/intc/arm_gicv3: Implement GICv3 CPU interface registers, Peter Maydell, 2016/05/09
- [Qemu-devel] [PATCH 23/23] RFC: hw/intc/arm_gicv3_kvm: Implement get/put functions, Peter Maydell, 2016/05/09
- [Qemu-devel] [PATCH 13/23] hw/intc/arm_gicv3: Wire up distributor and redistributor MMIO regions, Peter Maydell, 2016/05/09
- [Qemu-devel] [PATCH 01/23] migration: Define VMSTATE_UINT64_2DARRAY, Peter Maydell, 2016/05/09
- [Qemu-devel] [PATCH 06/23] hw/intc/arm_gicv3: Add state information, Peter Maydell, 2016/05/09
- [Qemu-devel] [PATCH 14/23] hw/intc/arm_gicv3: Implement gicv3_set_irq(), Peter Maydell, 2016/05/09
- [Qemu-devel] [PATCH 11/23] hw/intc/arm_gicv3: Implement GICv3 distributor registers, Peter Maydell, 2016/05/09