[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-devel] [PATCH v7 08/25] x86-iommu: introduce parent class
From: |
David Kiarie |
Subject: |
Re: [Qemu-devel] [PATCH v7 08/25] x86-iommu: introduce parent class |
Date: |
Tue, 24 May 2016 14:02:11 +0300 |
On Tue, May 24, 2016 at 1:40 PM, Jan Kiszka <address@hidden> wrote:
> On 2016-05-23 23:48, Marcel Apfelbaum wrote:
>> On 05/23/2016 08:06 PM, David Kiarie wrote:
>>> On Tue, May 17, 2016 at 10:15 AM, Peter Xu <address@hidden> wrote:
>>>> Introducing parent class for intel-iommu devices named "x86-iommu". This
>>>> is preparation work to abstract shared functionalities out from Intel
>>>> and AMD IOMMUs. Currently, only the parent class is introduced. It does
>>>> nothing yet.
>>>>
>>>> Signed-off-by: Peter Xu <address@hidden>
>>>> ---
>>>> hw/i386/Makefile.objs | 2 +-
>>
>> [...]
>>
>>>> +
>>>> +static const TypeInfo x86_iommu_info = {
>>>> + .name = TYPE_X86_IOMMU_DEVICE,
>>>> + .parent = TYPE_SYS_BUS_DEVICE,
>>>> + .instance_size = sizeof(X86IOMMUState),
>>>> + .class_init = x86_iommu_class_init,
>>>> + .class_size = sizeof(X86IOMMUClass),
>>>> + .abstract = true,
>>>> +};
>>>
>>> As I suspected am having some trouble parenting a PCI device from a
>>> Bus device but I will investigate further to see if I can manage
>>> something.
>>>
>>
>> You cannot derive from both SYS_BUS_DEVICE and PCI_DEVICE.
>> You would need a composition; your device would be a SYS_BUS_DEVICE
>> and its state would include a PCI_DEVICE (or the other way around).
>> Then you can divide the responsibilities between them.
>
> Given that the AMD IOMMU is more a platform than a PCI device, I would
> also go for deriving from SYS_BUS_DEVICE (and later on a common x86
> IOMMU class) and embedding a PCI_DEVICE. And the Intel IOMMU has no PCI
> device feature at all.
Yes, I managed to do that by getting rid of PCI device specific
callbacks(replaced them with DeviceState callbacks) so I get a compile
and no runtime fatality but device(AMD IOMMU) never appears in the
device tree.
>
> Jan
>
>
- [Qemu-devel] [PATCH v7 01/25] acpi: enable INTR for DMAR report structure, (continued)
- [Qemu-devel] [PATCH v7 01/25] acpi: enable INTR for DMAR report structure, Peter Xu, 2016/05/17
- [Qemu-devel] [PATCH v7 03/25] intel_iommu: set IR bit for ECAP register, Peter Xu, 2016/05/17
- [Qemu-devel] [PATCH v7 02/25] intel_iommu: allow queued invalidation for IR, Peter Xu, 2016/05/17
- [Qemu-devel] [PATCH v7 05/25] intel_iommu: define interrupt remap table addr register, Peter Xu, 2016/05/17
- [Qemu-devel] [PATCH v7 04/25] acpi: add DMAR scope definition for root IOAPIC, Peter Xu, 2016/05/17
- [Qemu-devel] [PATCH v7 06/25] intel_iommu: handle interrupt remap enable, Peter Xu, 2016/05/17
- [Qemu-devel] [PATCH v7 08/25] x86-iommu: introduce parent class, Peter Xu, 2016/05/17
[Qemu-devel] [PATCH v7 07/25] intel_iommu: define several structs for IOMMU IR, Peter Xu, 2016/05/17
- Re: [Qemu-devel] [PATCH v7 07/25] intel_iommu: define several structs for IOMMU IR, David Kiarie, 2016/05/29
- Re: [Qemu-devel] [PATCH v7 07/25] intel_iommu: define several structs for IOMMU IR, David Kiarie, 2016/05/29
- Re: [Qemu-devel] [PATCH v7 07/25] intel_iommu: define several structs for IOMMU IR, Peter Xu, 2016/05/30
- Re: [Qemu-devel] [PATCH v7 07/25] intel_iommu: define several structs for IOMMU IR, Jan Kiszka, 2016/05/30
- Re: [Qemu-devel] [PATCH v7 07/25] intel_iommu: define several structs for IOMMU IR, Peter Xu, 2016/05/30
- Re: [Qemu-devel] [PATCH v7 07/25] intel_iommu: define several structs for IOMMU IR, David Kiarie, 2016/05/30
- Re: [Qemu-devel] [PATCH v7 07/25] intel_iommu: define several structs for IOMMU IR, Peter Xu, 2016/05/30
- Re: [Qemu-devel] [PATCH v7 07/25] intel_iommu: define several structs for IOMMU IR, David Kiarie, 2016/05/30