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Re: [Qemu-devel] [Qemu-ppc] [PATCH 07/12] ppc: Better figure out if proc
From: |
Cédric Le Goater |
Subject: |
Re: [Qemu-devel] [Qemu-ppc] [PATCH 07/12] ppc: Better figure out if processor has HV mode |
Date: |
Fri, 27 May 2016 10:10:40 +0200 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Icedove/38.8.0 |
On 05/27/2016 06:41 AM, Thomas Huth wrote:
> On 27.05.2016 05:38, David Gibson wrote:
>> On Tue, May 03, 2016 at 06:03:29PM +0200, Cédric Le Goater wrote:
>>> From: Benjamin Herrenschmidt <address@hidden>
>>>
>>> We use an env. flag which is set to the initial value of MSR_HVB in
>>> the msr_mask. We also adjust the POWER8 mask to set SHV.
>>>
>>> Also use this to adjust ctx.hv so that it is *set* when the processor
>>> doesn't have an HV mode (970 with Apple mode for example), thus enabling
>>> hypervisor instructions/SPRs.
>>>
>>> Signed-off-by: Benjamin Herrenschmidt <address@hidden>
>>> Reviewed-by: David Gibson <address@hidden>
>>> ---
>>> target-ppc/cpu.h | 4 ++++
>>> target-ppc/translate.c | 4 +++-
>>> target-ppc/translate_init.c | 21 ++++++++++++++++-----
>>> 3 files changed, 23 insertions(+), 6 deletions(-)
> ...
>>> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
>>> index 10a92fdbbdd7..df656e6021b4 100644
>>> --- a/target-ppc/translate_init.c
>>> +++ b/target-ppc/translate_init.c
>>> @@ -8579,7 +8579,8 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
>>> PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
>>> PPC2_TM;
>>> pcc->msr_mask = (1ull << MSR_SF) |
>>> - (1ull << MSR_TM) |
>>> + (1ull << MSR_SHV) |
>>> + (1ull << MSR_TM) |
>>> (1ull << MSR_VR) |
>>> (1ull << MSR_VSX) |
>>> (1ull << MSR_EE) |
>
> This indentation looks somewhat suspicious ... and indeed, checkpatch
> compains here:
>
> ERROR: code indent should never use tabs
> #153: FILE: target-ppc/translate_init.c:8583:
> +^I^I (1ull << MSR_TM) |$
>
> total: 1 errors, 0 warnings, 60 lines checked
>
> Please fix it to use spaces instead.
Sure. I will. Thanks for checking. A couple of other patches for PowerNV
are in the same state.
Sometimes I wish I had a reasonable 'indent' command line.
C.
- [Qemu-devel] [PATCH 00/12] ppc: preparing pnv landing (round 2), Cédric Le Goater, 2016/05/03
- [Qemu-devel] [PATCH 03/12] ppc: Do some batching of TCG tlb flushes, Cédric Le Goater, 2016/05/03
- [Qemu-devel] [PATCH 05/12] ppc: Fix hreg_store_msr() so that non-HV mode cannot alter MSR:HV, Cédric Le Goater, 2016/05/03
- [Qemu-devel] [PATCH 08/12] ppc: tlbie, tlbia and tlbisync are HV only, Cédric Le Goater, 2016/05/03
- [Qemu-devel] [PATCH 10/12] ppc: Fix sign extension issue in mtmsr(d) emulation, Cédric Le Goater, 2016/05/03
- [Qemu-devel] [PATCH 06/12] ppc: Fix rfi/rfid/hrfi/... emulation, Cédric Le Goater, 2016/05/03
- [Qemu-devel] [PATCH 07/12] ppc: Better figure out if processor has HV mode, Cédric Le Goater, 2016/05/03
[Qemu-devel] [PATCH 01/12] ppc: Remove MMU_MODEn_SUFFIX definitions, Cédric Le Goater, 2016/05/03
[Qemu-devel] [PATCH 11/12] ppc: Get out of emulation on SMT "OR" ops, Cédric Le Goater, 2016/05/03
[Qemu-devel] [PATCH 12/12] ppc: Add PPC_64H instruction flag to POWER7 and POWER8, Cédric Le Goater, 2016/05/03
[Qemu-devel] [PATCH 04/12] ppc: Add a bunch of hypervisor SPRs to Book3s, Cédric Le Goater, 2016/05/03
[Qemu-devel] [PATCH 09/12] ppc: Change 'invalid' bit mask of tlbiel and tlbie, Cédric Le Goater, 2016/05/03
[Qemu-devel] [PATCH 02/12] ppc: Use split I/D mmu modes to avoid flushes on interrupts, Cédric Le Goater, 2016/05/03
Re: [Qemu-devel] [PATCH 00/12] ppc: preparing pnv landing (round 2), David Gibson, 2016/05/03