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[Qemu-devel] [PATCH 4/4] target-tricore: Added new JNE instruction varia
From: |
peer . adelt |
Subject: |
[Qemu-devel] [PATCH 4/4] target-tricore: Added new JNE instruction variant |
Date: |
Mon, 30 May 2016 00:59:28 +0200 |
From: Peer Adelt <address@hidden>
If D[15] is != sign_ext(const4) then PC will be set to (PC +
zero_ext(disp4 + 16)).
Signed-off-by: Peer Adelt <address@hidden>
---
target-tricore/translate.c | 1 +
target-tricore/tricore-opcodes.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 2145f64..9ad9fcc 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -3363,6 +3363,7 @@ static void gen_compute_branch(DisasContext *ctx,
uint32_t opc, int r1,
gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant, offset);
break;
case OPC1_16_SBC_JNE:
+ case OPC1_16_SBC_JNE16:
gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], constant, offset);
break;
/* SBRN-format jumps */
diff --git a/target-tricore/tricore-opcodes.h b/target-tricore/tricore-opcodes.h
index 2f25613..7925354 100644
--- a/target-tricore/tricore-opcodes.h
+++ b/target-tricore/tricore-opcodes.h
@@ -318,6 +318,7 @@ enum {
OPC1_16_SBR_JLEZ = 0x8e,
OPC1_16_SBR_JLTZ = 0x0e,
OPC1_16_SBC_JNE = 0x5e,
+ OPC1_16_SBC_JNE16 = 0xde,
OPC1_16_SBR_JNE = 0x7e,
OPC1_16_SB_JNZ = 0xee,
OPC1_16_SBR_JNZ = 0xf6,
--
2.7.4 (Apple Git-66)