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Re: [Qemu-devel] [PATCH v2 3/4] target-tricore: Added new MOV instructio
From: |
Bastian Koppelmann |
Subject: |
Re: [Qemu-devel] [PATCH v2 3/4] target-tricore: Added new MOV instruction variant |
Date: |
Tue, 31 May 2016 10:49:34 +0200 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.1.0 |
On 05/31/2016 07:48 AM, address@hidden wrote:
> From: Peer Adelt <address@hidden>
>
> Puts the content of data register D[a] into E[c][63:32] and the
> content of data register D[b] into E[c][31:0].
>
> Signed-off-by: Peer Adelt <address@hidden>
> ---
> target-tricore/translate.c | 8 ++++++++
> target-tricore/tricore-opcodes.h | 1 +
> 2 files changed, 9 insertions(+)
>
> diff --git a/target-tricore/translate.c b/target-tricore/translate.c
> index e66b433..960ee33 100644
> --- a/target-tricore/translate.c
> +++ b/target-tricore/translate.c
> @@ -6224,6 +6224,14 @@ static void decode_rr_accumulator(CPUTriCoreState
> *env, DisasContext *ctx)
> case OPC2_32_RR_MOV:
> tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]);
> break;
> + case OPC2_32_RR_MOV_EXT:
> + if (tricore_feature(env, TRICORE_FEATURE_16)) {
> + tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
> + tcg_gen_mov_tl(cpu_gpr_d[(r3+1)], cpu_gpr_d[r2]);
If r2 == r3 you would move r1 into r3+1 which is wrong. Use temporaries
instead of directly writing to r3.
Cheers,
Bastian