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[Qemu-devel] [PATCH v4 0/9] 8bit AVR cores
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From: |
Michael Rolnik |
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Subject: |
[Qemu-devel] [PATCH v4 0/9] 8bit AVR cores |
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Date: |
Mon, 6 Jun 2016 13:37:51 +0300 |
This series of patches adds 8bit AVR cores to QEMU.
All instruction, except BREAK/DES/SPM/SPMX, are implemented. Not fully tested
yet.
However I was able to execute simple code with functions. e.g fibonacci
calculation.
This series of patches include a non real, sample board.
No fuses support yet. PC is set to 0 at reset.
the patches include the following
1. just a basic 8bit AVR CPU, without instruction decoding or translation
2. CPU features which allow define the following 8bit AVR cores
avr1
avr2 avr25
avr3 avr31 avr35
avr4
avr5 avr51
avr6
xmega2 xmega4 xmega5 xmega6 xmega7
3. a definition of sample machine with SRAM, FLASH and CPU which allows to
execute simple code
4. encoding for all AVR instructions
5. interrupt handling
6. helpers for IN, OUT, SLEEP, WBR & unsupported instructions
7. a decoder which given an opcode decides what istruction it is
8. translation of AVR instruction into TCG
9. all features together
changes since v3
1. rampD/X/Y/Z registers are encoded as 0x00ff0000 and not 0x000000ff for
faster address manipulaton
2. ffs changed to ctz32
3. duplicate code removed at avr_cpu_do_interrupt
4. using andc instead of not + and
5. fixing V flag calculation in varios instructions
6. freeing local variables in PUSH
7. tcg_const_local_i32 -> tcg_const_i32
8. using sextract32 instead of my implementation
9. fixing BLD instruction
10.xor(r) instead of 0xff - r at COM
11.fixing MULS/MULSU not to modify inputs' content
12.using SUB for NEG
13.fixing tcg_gen_qemu_ld/st call in XCH
A big thanks to Richard Henderson for the review.
Michael Rolnik (9):
target-avr: AVR cores support is added. 1. basic CPU
structure 2. registers 3. no instructions
target-avr: adding AVR CPU features/flavors
target-avr: adding a sample AVR board
target-avr: adding instructions encodings
target-avr: adding AVR interrupt handling
target-avr: adding helpers for IN, OUT, SLEEP, WBR & unsupported
instructions
target-avr: adding instruction decoder
target-avr: adding instruction translation
target-avr: updating translate.c to use instructions translation
arch_init.c | 2 +
configure | 5 +
default-configs/avr-softmmu.mak | 1 +
disas/Makefile.objs | 1 +
disas/avr.c | 10 +
hw/Makefile.objs | 1 +
hw/avr/Makefile.objs | 1 +
hw/avr/sample-io.c | 217 ++++
hw/avr/sample.c | 118 ++
include/disas/bfd.h | 7 +
include/sysemu/arch_init.h | 1 +
target-avr/Makefile.objs | 5 +
target-avr/cpu-qom.h | 80 ++
target-avr/cpu.c | 595 ++++++++++
target-avr/cpu.h | 193 +++
target-avr/decode.c | 724 ++++++++++++
target-avr/gdbstub.c | 99 ++
target-avr/helper.c | 273 +++++
target-avr/helper.h | 26 +
target-avr/machine.c | 54 +
target-avr/machine.h | 21 +
target-avr/translate-inst.c | 2499 +++++++++++++++++++++++++++++++++++++++
target-avr/translate-inst.h | 730 ++++++++++++
target-avr/translate.c | 268 +++++
target-avr/translate.h | 120 ++
25 files changed, 6051 insertions(+)
create mode 100644 default-configs/avr-softmmu.mak
create mode 100644 disas/avr.c
create mode 100644 hw/avr/Makefile.objs
create mode 100644 hw/avr/sample-io.c
create mode 100644 hw/avr/sample.c
create mode 100644 target-avr/Makefile.objs
create mode 100644 target-avr/cpu-qom.h
create mode 100644 target-avr/cpu.c
create mode 100644 target-avr/cpu.h
create mode 100644 target-avr/decode.c
create mode 100644 target-avr/gdbstub.c
create mode 100644 target-avr/helper.c
create mode 100644 target-avr/helper.h
create mode 100644 target-avr/machine.c
create mode 100644 target-avr/machine.h
create mode 100644 target-avr/translate-inst.c
create mode 100644 target-avr/translate-inst.h
create mode 100644 target-avr/translate.c
create mode 100644 target-avr/translate.h
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