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[Qemu-devel] [PATCH v9 16/25] intel_iommu: add support for split irqchip
From: |
Peter Xu |
Subject: |
[Qemu-devel] [PATCH v9 16/25] intel_iommu: add support for split irqchip |
Date: |
Mon, 13 Jun 2016 21:09:32 +0800 |
In split irqchip mode, IOAPIC is working in user space, only update
kernel irq routes when entry changed. When IR is enabled, we directly
update the kernel with translated messages. It works just like a kernel
cache for the remapping entries.
Since KVM irqfd is using kernel gsi routes to deliver interrupts, as
long as we can support split irqchip, we will support irqfd as
well. Also, since kernel gsi routes will cache translated interrupts,
irqfd delivery will not suffer from any performance impact due to IR.
And, since we supported irqfd, vhost devices will be able to work
seamlessly with IR now. Logically this should contain both vhost-net and
vhost-user case.
Signed-off-by: Peter Xu <address@hidden>
---
hw/i386/intel_iommu.c | 7 +++++++
include/hw/i386/intel_iommu.h | 1 +
include/hw/i386/x86-iommu.h | 4 ++++
target-i386/kvm.c | 27 +++++++++++++++++++++++++++
trace-events | 3 +++
5 files changed, 42 insertions(+)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index d874596..0eaffc6 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -2149,6 +2149,12 @@ do_not_translate:
return 0;
}
+static int vtd_int_remap(X86IOMMUState *iommu, MSIMessage *src,
+ MSIMessage *dst, uint16_t sid)
+{
+ return vtd_interrupt_remap_msi(INTEL_IOMMU_DEVICE(iommu), src, dst);
+}
+
static MemTxResult vtd_mem_ir_read(void *opaque, hwaddr addr,
uint64_t *data, unsigned size,
MemTxAttrs attrs)
@@ -2393,6 +2399,7 @@ static void vtd_class_init(ObjectClass *klass, void *data)
dc->props = vtd_properties;
x86_class->realize = vtd_realize;
x86_class->find_add_as = vtd_find_add_as;
+ x86_class->int_remap = vtd_int_remap;
}
static const TypeInfo vtd_info = {
diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h
index b3f17d7..3bca390 100644
--- a/include/hw/i386/intel_iommu.h
+++ b/include/hw/i386/intel_iommu.h
@@ -26,6 +26,7 @@
#include "hw/i386/x86-iommu.h"
#include "hw/i386/ioapic.h"
#include "hw/pci/msi.h"
+#include "hw/sysbus.h"
#define TYPE_INTEL_IOMMU_DEVICE "intel-iommu"
#define INTEL_IOMMU_DEVICE(obj) \
diff --git a/include/hw/i386/x86-iommu.h b/include/hw/i386/x86-iommu.h
index 07199be..b419ae5 100644
--- a/include/hw/i386/x86-iommu.h
+++ b/include/hw/i386/x86-iommu.h
@@ -22,6 +22,7 @@
#include "hw/sysbus.h"
#include "exec/memory.h"
+#include "hw/pci/pci.h"
#define TYPE_X86_IOMMU_DEVICE ("x86-iommu")
#define X86_IOMMU_DEVICE(obj) \
@@ -43,6 +44,9 @@ struct X86IOMMUClass {
DeviceRealize realize;
/* Find/Add IOMMU address space for specific PCI device */
AddressSpace *(*find_add_as)(X86IOMMUState *s, PCIBus *bus, int devfn);
+ /* MSI-based interrupt remapping */
+ int (*int_remap)(X86IOMMUState *iommu, MSIMessage *src,
+ MSIMessage *dst, uint16_t sid);
};
struct X86IOMMUState {
diff --git a/target-i386/kvm.c b/target-i386/kvm.c
index abf50e6..57949e0 100644
--- a/target-i386/kvm.c
+++ b/target-i386/kvm.c
@@ -36,6 +36,7 @@
#include "hw/i386/apic.h"
#include "hw/i386/apic_internal.h"
#include "hw/i386/apic-msidef.h"
+#include "hw/i386/intel_iommu.h"
#include "exec/ioport.h"
#include "standard-headers/asm-x86/hyperv.h"
@@ -43,6 +44,7 @@
#include "hw/pci/msi.h"
#include "migration/migration.h"
#include "exec/memattrs.h"
+#include "trace.h"
//#define DEBUG_KVM
@@ -3320,6 +3322,31 @@ int kvm_device_msix_deassign(KVMState *s, uint32_t
dev_id)
int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
uint64_t address, uint32_t data, PCIDevice *dev)
{
+ X86IOMMUState *iommu = x86_iommu_get_default();
+
+ if (iommu) {
+ int ret;
+ MSIMessage src, dst;
+ X86IOMMUClass *class = X86_IOMMU_GET_CLASS(iommu);
+
+ src.address = route->u.msi.address_hi;
+ src.address <<= VTD_MSI_ADDR_HI_SHIFT;
+ src.address |= route->u.msi.address_lo;
+ src.data = route->u.msi.data;
+
+ ret = class->int_remap(iommu, &src, &dst, dev ? \
+ pci_requester_id(dev) : \
+ X86_IOMMU_SID_INVALID);
+ if (ret) {
+ trace_kvm_x86_fixup_msi_error(route->gsi);
+ return 1;
+ }
+
+ route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
+ route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
+ route->u.msi.data = dst.data;
+ }
+
return 0;
}
diff --git a/trace-events b/trace-events
index 421d89f..4d2a9ef 100644
--- a/trace-events
+++ b/trace-events
@@ -2163,3 +2163,6 @@ e1000e_cfg_support_virtio(bool support) "Virtio header
supported: %d"
e1000e_vm_state_running(void) "VM state is running"
e1000e_vm_state_stopped(void) "VM state is stopped"
+
+# target-i386/kvm.c
+kvm_x86_fixup_msi_error(uint32_t gsi) "VT-d failed to remap interrupt for GSI
%" PRIu32
--
2.4.11
- [Qemu-devel] [PATCH v9 05/25] acpi: enable INTR for DMAR report structure, (continued)
- [Qemu-devel] [PATCH v9 05/25] acpi: enable INTR for DMAR report structure, Peter Xu, 2016/06/13
- [Qemu-devel] [PATCH v9 07/25] intel_iommu: set IR bit for ECAP register, Peter Xu, 2016/06/13
- [Qemu-devel] [PATCH v9 08/25] acpi: add DMAR scope definition for root IOAPIC, Peter Xu, 2016/06/13
- [Qemu-devel] [PATCH v9 10/25] intel_iommu: handle interrupt remap enable, Peter Xu, 2016/06/13
- [Qemu-devel] [PATCH v9 09/25] intel_iommu: define interrupt remap table addr register, Peter Xu, 2016/06/13
- [Qemu-devel] [PATCH v9 12/25] intel_iommu: add IR translation faults defines, Peter Xu, 2016/06/13
- [Qemu-devel] [PATCH v9 11/25] intel_iommu: define several structs for IOMMU IR, Peter Xu, 2016/06/13
- [Qemu-devel] [PATCH v9 13/25] intel_iommu: Add support for PCI MSI remap, Peter Xu, 2016/06/13
- [Qemu-devel] [PATCH v9 14/25] q35: ioapic: add support for emulated IOAPIC IR, Peter Xu, 2016/06/13
- [Qemu-devel] [PATCH v9 15/25] ioapic: introduce ioapic_entry_parse() helper, Peter Xu, 2016/06/13
- [Qemu-devel] [PATCH v9 16/25] intel_iommu: add support for split irqchip,
Peter Xu <=
- [Qemu-devel] [PATCH v9 17/25] x86-iommu: introduce IEC notifiers, Peter Xu, 2016/06/13
- [Qemu-devel] [PATCH v9 18/25] ioapic: register IOMMU IEC notifier for ioapic, Peter Xu, 2016/06/13
- [Qemu-devel] [PATCH v9 19/25] intel_iommu: Add support for Extended Interrupt Mode, Peter Xu, 2016/06/13
- [Qemu-devel] [PATCH v9 20/25] intel_iommu: add SID validation for IR, Peter Xu, 2016/06/13
- [Qemu-devel] [PATCH v9 21/25] kvm-irqchip: simplify kvm_irqchip_add_msi_route, Peter Xu, 2016/06/13
- [Qemu-devel] [PATCH v9 22/25] kvm-irqchip: i386: add hook for add/remove virq, Peter Xu, 2016/06/13
- [Qemu-devel] [PATCH v9 23/25] kvm-irqchip: x86: add msi route notify fn, Peter Xu, 2016/06/13
- [Qemu-devel] [PATCH v9 24/25] kvm-irqchip: do explicit commit when update irq, Peter Xu, 2016/06/13
- [Qemu-devel] [PATCH v9 25/25] intel_iommu: support all masks in interrupt entry cache invalidation, Peter Xu, 2016/06/13