[Qemu-devel] [RFC PATCH 08/11] zynqmp_crf: fix against AF_EX32 changes

[fred . konrad]

From: KONRAD Frederic <address@hidden>

This seems to be due to a difference between the AF_EX32 define.

Signed-off-by: KONRAD Frederic <address@hidden>
---
 hw/misc/xilinx_zynqmp_crf.c | 354 ++++++++++++++++++++++----------------------
 1 file changed, 177 insertions(+), 177 deletions(-)

diff --git a/hw/misc/xilinx_zynqmp_crf.c b/hw/misc/xilinx_zynqmp_crf.c
index b1bf2a6..4c670a0 100644
--- a/hw/misc/xilinx_zynqmp_crf.c
+++ b/hw/misc/xilinx_zynqmp_crf.c
@@ -41,236 +41,236 @@
      OBJECT_CHECK(CRF_APB, (obj), TYPE_XILINX_CRF_APB)
 
 REG32(ERR_CTRL, 0x0)
-    FIELD(ERR_CTRL, SLVERR_ENABLE, 1, 0)
+    FIELD(ERR_CTRL, SLVERR_ENABLE, 0, 1)
 REG32(IR_STATUS, 0x4)
-    FIELD(IR_STATUS, ADDR_DECODE_ERR, 1, 0)
+    FIELD(IR_STATUS, ADDR_DECODE_ERR, 0, 1)
 REG32(IR_MASK, 0x8)
-    FIELD(IR_MASK, ADDR_DECODE_ERR, 1, 0)
+    FIELD(IR_MASK, ADDR_DECODE_ERR, 0, 1)
 REG32(IR_ENABLE, 0xc)
-    FIELD(IR_ENABLE, ADDR_DECODE_ERR, 1, 0)
+    FIELD(IR_ENABLE, ADDR_DECODE_ERR, 0, 1)
 REG32(IR_DISABLE, 0x10)
-    FIELD(IR_DISABLE, ADDR_DECODE_ERR, 1, 0)
+    FIELD(IR_DISABLE, ADDR_DECODE_ERR, 0, 1)
 REG32(CRF_ECO, 0x18)
 REG32(APLL_CTRL, 0x20)
-    FIELD(APLL_CTRL, POST_SRC, 3, 24)
-    FIELD(APLL_CTRL, PRE_SRC, 3, 20)
-    FIELD(APLL_CTRL, CLKOUTDIV, 1, 17)
-    FIELD(APLL_CTRL, DIV2, 1, 16)
-    FIELD(APLL_CTRL, FBDIV, 7, 8)
-    FIELD(APLL_CTRL, BYPASS, 1, 3)
-    FIELD(APLL_CTRL, RESET, 1, 0)
+    FIELD(APLL_CTRL, POST_SRC, 24, 3)
+    FIELD(APLL_CTRL, PRE_SRC, 20, 3)
+    FIELD(APLL_CTRL, CLKOUTDIV, 17, 1)
+    FIELD(APLL_CTRL, DIV2, 16, 1)
+    FIELD(APLL_CTRL, FBDIV, 8, 7)
+    FIELD(APLL_CTRL, BYPASS, 3, 1)
+    FIELD(APLL_CTRL, RESET, 0, 1)
 REG32(APLL_CFG, 0x24)
-    FIELD(APLL_CFG, LOCK_DLY, 7, 25)
-    FIELD(APLL_CFG, LOCK_CNT, 10, 13)
-    FIELD(APLL_CFG, LFHF, 2, 10)
-    FIELD(APLL_CFG, CP, 4, 5)
-    FIELD(APLL_CFG, RES, 4, 0)
+    FIELD(APLL_CFG, LOCK_DLY, 25, 7)
+    FIELD(APLL_CFG, LOCK_CNT, 13, 10)
+    FIELD(APLL_CFG, LFHF, 10, 2)
+    FIELD(APLL_CFG, CP, 5, 4)
+    FIELD(APLL_CFG, RES, 0, 4)
 REG32(APLL_FRAC_CFG, 0x28)
-    FIELD(APLL_FRAC_CFG, ENABLED, 1, 31)
-    FIELD(APLL_FRAC_CFG, SEED, 3, 22)
-    FIELD(APLL_FRAC_CFG, ALGRTHM, 1, 19)
-    FIELD(APLL_FRAC_CFG, ORDER, 1, 18)
-    FIELD(APLL_FRAC_CFG, DATA, 16, 0)
+    FIELD(APLL_FRAC_CFG, ENABLED, 31, 1)
+    FIELD(APLL_FRAC_CFG, SEED, 22, 3)
+    FIELD(APLL_FRAC_CFG, ALGRTHM, 19, 1)
+    FIELD(APLL_FRAC_CFG, ORDER, 18, 1)
+    FIELD(APLL_FRAC_CFG, DATA, 0, 16)
 REG32(DPLL_CTRL, 0x2c)
-    FIELD(DPLL_CTRL, POST_SRC, 3, 24)
-    FIELD(DPLL_CTRL, PRE_SRC, 3, 20)
-    FIELD(DPLL_CTRL, CLKOUTDIV, 1, 17)
-    FIELD(DPLL_CTRL, DIV2, 1, 16)
-    FIELD(DPLL_CTRL, FBDIV, 7, 8)
-    FIELD(DPLL_CTRL, BYPASS, 1, 3)
-    FIELD(DPLL_CTRL, RESET, 1, 0)
+    FIELD(DPLL_CTRL, POST_SRC, 24, 3)
+    FIELD(DPLL_CTRL, PRE_SRC, 20, 3)
+    FIELD(DPLL_CTRL, CLKOUTDIV, 17, 1)
+    FIELD(DPLL_CTRL, DIV2, 16, 1)
+    FIELD(DPLL_CTRL, FBDIV, 8, 7)
+    FIELD(DPLL_CTRL, BYPASS, 3, 1)
+    FIELD(DPLL_CTRL, RESET, 0, 1)
 REG32(DPLL_CFG, 0x30)
-    FIELD(DPLL_CFG, LOCK_DLY, 7, 25)
-    FIELD(DPLL_CFG, LOCK_CNT, 10, 13)
-    FIELD(DPLL_CFG, LFHF, 2, 10)
-    FIELD(DPLL_CFG, CP, 4, 5)
-    FIELD(DPLL_CFG, RES, 4, 0)
+    FIELD(DPLL_CFG, LOCK_DLY, 25, 7)
+    FIELD(DPLL_CFG, LOCK_CNT, 13, 10)
+    FIELD(DPLL_CFG, LFHF, 10, 2)
+    FIELD(DPLL_CFG, CP, 5, 4)
+    FIELD(DPLL_CFG, RES, 0, 4)
 REG32(DPLL_FRAC_CFG, 0x34)
-    FIELD(DPLL_FRAC_CFG, ENABLED, 1, 31)
-    FIELD(DPLL_FRAC_CFG, SEED, 3, 22)
-    FIELD(DPLL_FRAC_CFG, ALGRTHM, 1, 19)
-    FIELD(DPLL_FRAC_CFG, ORDER, 1, 18)
-    FIELD(DPLL_FRAC_CFG, DATA, 16, 0)
+    FIELD(DPLL_FRAC_CFG, ENABLED, 31, 1)
+    FIELD(DPLL_FRAC_CFG, SEED, 22, 3)
+    FIELD(DPLL_FRAC_CFG, ALGRTHM, 19, 1)
+    FIELD(DPLL_FRAC_CFG, ORDER, 18, 1)
+    FIELD(DPLL_FRAC_CFG, DATA, 0, 16)
 REG32(VPLL_CTRL, 0x38)
-    FIELD(VPLL_CTRL, POST_SRC, 3, 24)
-    FIELD(VPLL_CTRL, PRE_SRC, 3, 20)
-    FIELD(VPLL_CTRL, CLKOUTDIV, 1, 17)
-    FIELD(VPLL_CTRL, DIV2, 1, 16)
-    FIELD(VPLL_CTRL, FBDIV, 7, 8)
-    FIELD(VPLL_CTRL, BYPASS, 1, 3)
-    FIELD(VPLL_CTRL, RESET, 1, 0)
+    FIELD(VPLL_CTRL, POST_SRC, 24, 3)
+    FIELD(VPLL_CTRL, PRE_SRC, 20, 3)
+    FIELD(VPLL_CTRL, CLKOUTDIV, 17, 1)
+    FIELD(VPLL_CTRL, DIV2, 16, 1)
+    FIELD(VPLL_CTRL, FBDIV, 8, 7)
+    FIELD(VPLL_CTRL, BYPASS, 3, 1)
+    FIELD(VPLL_CTRL, RESET, 0, 1)
 REG32(VPLL_CFG, 0x3c)
-    FIELD(VPLL_CFG, LOCK_DLY, 7, 25)
-    FIELD(VPLL_CFG, LOCK_CNT, 10, 13)
-    FIELD(VPLL_CFG, LFHF, 2, 10)
-    FIELD(VPLL_CFG, CP, 4, 5)
-    FIELD(VPLL_CFG, RES, 4, 0)
+    FIELD(VPLL_CFG, LOCK_DLY, 25, 7)
+    FIELD(VPLL_CFG, LOCK_CNT, 13, 10)
+    FIELD(VPLL_CFG, LFHF, 10, 2)
+    FIELD(VPLL_CFG, CP, 5, 4)
+    FIELD(VPLL_CFG, RES, 0, 4)
 REG32(VPLL_FRAC_CFG, 0x40)
-    FIELD(VPLL_FRAC_CFG, ENABLED, 1, 31)
-    FIELD(VPLL_FRAC_CFG, SEED, 3, 22)
-    FIELD(VPLL_FRAC_CFG, ALGRTHM, 1, 19)
-    FIELD(VPLL_FRAC_CFG, ORDER, 1, 18)
-    FIELD(VPLL_FRAC_CFG, DATA, 16, 0)
+    FIELD(VPLL_FRAC_CFG, ENABLED, 31, 1)
+    FIELD(VPLL_FRAC_CFG, SEED, 22, 3)
+    FIELD(VPLL_FRAC_CFG, ALGRTHM, 19, 1)
+    FIELD(VPLL_FRAC_CFG, ORDER, 18, 1)
+    FIELD(VPLL_FRAC_CFG, DATA, 0, 16)
 REG32(PLL_STATUS, 0x44)
-    FIELD(PLL_STATUS, VPLL_STABLE, 1, 5)
-    FIELD(PLL_STATUS, DPLL_STABLE, 1, 4)
-    FIELD(PLL_STATUS, APLL_STABLE, 1, 3)
-    FIELD(PLL_STATUS, VPLL_LOCK, 1, 2)
+    FIELD(PLL_STATUS, VPLL_STABLE, 5, 1)
+    FIELD(PLL_STATUS, DPLL_STABLE, 4, 1)
+    FIELD(PLL_STATUS, APLL_STABLE, 3, 1)
+    FIELD(PLL_STATUS, VPLL_LOCK, 2, 1)
     FIELD(PLL_STATUS, DPLL_LOCK, 1, 1)
-    FIELD(PLL_STATUS, APLL_LOCK, 1, 0)
+    FIELD(PLL_STATUS, APLL_LOCK, 0, 1)
 REG32(APLL_TO_LPD_CTRL, 0x48)
-    FIELD(APLL_TO_LPD_CTRL, DIVISOR0, 6, 8)
+    FIELD(APLL_TO_LPD_CTRL, DIVISOR0, 8, 6)
 REG32(DPLL_TO_LPD_CTRL, 0x4c)
-    FIELD(DPLL_TO_LPD_CTRL, DIVISOR0, 6, 8)
+    FIELD(DPLL_TO_LPD_CTRL, DIVISOR0, 8, 6)
 REG32(VPLL_TO_LPD_CTRL, 0x50)
-    FIELD(VPLL_TO_LPD_CTRL, DIVISOR0, 6, 8)
+    FIELD(VPLL_TO_LPD_CTRL, DIVISOR0, 8, 6)
 REG32(CPU_A9_CTRL, 0x60)
-    FIELD(CPU_A9_CTRL, A9CLKSTOP, 2, 26)
-    FIELD(CPU_A9_CTRL, CLKACT_HALF, 1, 25)
-    FIELD(CPU_A9_CTRL, CLKACT_FULL, 1, 24)
-    FIELD(CPU_A9_CTRL, DIVISOR0, 6, 8)
-    FIELD(CPU_A9_CTRL, SRCSEL, 3, 0)
+    FIELD(CPU_A9_CTRL, A9CLKSTOP, 26, 2)
+    FIELD(CPU_A9_CTRL, CLKACT_HALF, 25, 1)
+    FIELD(CPU_A9_CTRL, CLKACT_FULL, 24, 1)
+    FIELD(CPU_A9_CTRL, DIVISOR0, 8, 6)
+    FIELD(CPU_A9_CTRL, SRCSEL, 0, 3)
 REG32(DBG_TRACE_CTRL, 0x64)
-    FIELD(DBG_TRACE_CTRL, CLKACT, 1, 24)
-    FIELD(DBG_TRACE_CTRL, DIVISOR0, 6, 8)
-    FIELD(DBG_TRACE_CTRL, SRCSEL, 3, 0)
+    FIELD(DBG_TRACE_CTRL, CLKACT, 24, 1)
+    FIELD(DBG_TRACE_CTRL, DIVISOR0, 8, 6)
+    FIELD(DBG_TRACE_CTRL, SRCSEL, 0, 3)
 REG32(DBG_FPD_CTRL, 0x68)
-    FIELD(DBG_FPD_CTRL, CLKACT, 1, 24)
-    FIELD(DBG_FPD_CTRL, DIVISOR0, 6, 8)
-    FIELD(DBG_FPD_CTRL, SRCSEL, 3, 0)
+    FIELD(DBG_FPD_CTRL, CLKACT, 24, 1)
+    FIELD(DBG_FPD_CTRL, DIVISOR0, 8, 6)
+    FIELD(DBG_FPD_CTRL, SRCSEL, 0, 3)
 REG32(DP_VIDEO_REF_CTRL, 0x70)
-    FIELD(DP_VIDEO_REF_CTRL, CLKACT, 1, 24)
-    FIELD(DP_VIDEO_REF_CTRL, DIVISOR0, 6, 8)
-    FIELD(DP_VIDEO_REF_CTRL, SRCSEL, 3, 0)
+    FIELD(DP_VIDEO_REF_CTRL, CLKACT, 24, 1)
+    FIELD(DP_VIDEO_REF_CTRL, DIVISOR0, 8, 6)
+    FIELD(DP_VIDEO_REF_CTRL, SRCSEL, 0, 3)
 REG32(DP_AUDIO_REF_CTRL, 0x74)
-    FIELD(DP_AUDIO_REF_CTRL, CLKACT, 1, 24)
-    FIELD(DP_AUDIO_REF_CTRL, DIVISOR0, 6, 8)
-    FIELD(DP_AUDIO_REF_CTRL, SRCSEL, 3, 0)
+    FIELD(DP_AUDIO_REF_CTRL, CLKACT, 24, 1)
+    FIELD(DP_AUDIO_REF_CTRL, DIVISOR0, 8, 6)
+    FIELD(DP_AUDIO_REF_CTRL, SRCSEL, 0, 3)
 REG32(DP_LINK_REF_CTRL, 0x78)
-    FIELD(DP_LINK_REF_CTRL, CLKACT, 1, 24)
-    FIELD(DP_LINK_REF_CTRL, DIVISOR1, 6, 16)
-    FIELD(DP_LINK_REF_CTRL, DIVISOR0, 6, 8)
-    FIELD(DP_LINK_REF_CTRL, SRCSEL, 3, 0)
+    FIELD(DP_LINK_REF_CTRL, CLKACT, 24, 1)
+    FIELD(DP_LINK_REF_CTRL, DIVISOR1, 16, 6)
+    FIELD(DP_LINK_REF_CTRL, DIVISOR0, 8, 6)
+    FIELD(DP_LINK_REF_CTRL, SRCSEL, 0, 3)
 REG32(DP_STC_REF_CTRL, 0x7c)
-    FIELD(DP_STC_REF_CTRL, CLKACT, 1, 24)
-    FIELD(DP_STC_REF_CTRL, DIVISOR1, 6, 16)
-    FIELD(DP_STC_REF_CTRL, DIVISOR0, 6, 8)
-    FIELD(DP_STC_REF_CTRL, SRCSEL, 3, 0)
+    FIELD(DP_STC_REF_CTRL, CLKACT, 24, 1)
+    FIELD(DP_STC_REF_CTRL, DIVISOR1, 16, 6)
+    FIELD(DP_STC_REF_CTRL, DIVISOR0, 8, 6)
+    FIELD(DP_STC_REF_CTRL, SRCSEL, 0, 3)
 REG32(DDR_CTRL, 0x80)
-    FIELD(DDR_CTRL, CLKACT, 1, 24)
-    FIELD(DDR_CTRL, DIVISOR0, 6, 8)
-    FIELD(DDR_CTRL, SRCSEL, 3, 0)
+    FIELD(DDR_CTRL, CLKACT, 24, 1)
+    FIELD(DDR_CTRL, DIVISOR0, 8, 6)
+    FIELD(DDR_CTRL, SRCSEL, 0, 3)
 REG32(GPU_REF_CTRL, 0x84)
-    FIELD(GPU_REF_CTRL, PP1_CLKACT, 1, 26)
-    FIELD(GPU_REF_CTRL, PP0_CLKACT, 1, 25)
-    FIELD(GPU_REF_CTRL, CLKACT, 1, 24)
-    FIELD(GPU_REF_CTRL, DIVISOR0, 6, 8)
-    FIELD(GPU_REF_CTRL, SRCSEL, 3, 0)
+    FIELD(GPU_REF_CTRL, PP1_CLKACT, 26, 1)
+    FIELD(GPU_REF_CTRL, PP0_CLKACT, 25, 1)
+    FIELD(GPU_REF_CTRL, CLKACT, 24, 1)
+    FIELD(GPU_REF_CTRL, DIVISOR0, 8, 6)
+    FIELD(GPU_REF_CTRL, SRCSEL, 0, 3)
 REG32(AFI0_REF_CTRL, 0x88)
-    FIELD(AFI0_REF_CTRL, CLKACT, 1, 24)
-    FIELD(AFI0_REF_CTRL, DIVISOR0, 6, 8)
-    FIELD(AFI0_REF_CTRL, SRCSEL, 3, 0)
+    FIELD(AFI0_REF_CTRL, CLKACT, 24, 1)
+    FIELD(AFI0_REF_CTRL, DIVISOR0, 8, 6)
+    FIELD(AFI0_REF_CTRL, SRCSEL, 0, 3)
 REG32(AFI1_REF_CTRL, 0x8c)
-    FIELD(AFI1_REF_CTRL, CLKACT, 1, 24)
-    FIELD(AFI1_REF_CTRL, DIVISOR0, 6, 8)
-    FIELD(AFI1_REF_CTRL, SRCSEL, 3, 0)
+    FIELD(AFI1_REF_CTRL, CLKACT, 24, 1)
+    FIELD(AFI1_REF_CTRL, DIVISOR0, 8, 6)
+    FIELD(AFI1_REF_CTRL, SRCSEL, 0, 3)
 REG32(AFI2_REF_CTRL, 0x90)
-    FIELD(AFI2_REF_CTRL, CLKACT, 1, 24)
-    FIELD(AFI2_REF_CTRL, DIVISOR0, 6, 8)
-    FIELD(AFI2_REF_CTRL, SRCSEL, 3, 0)
+    FIELD(AFI2_REF_CTRL, CLKACT, 24, 1)
+    FIELD(AFI2_REF_CTRL, DIVISOR0, 8, 6)
+    FIELD(AFI2_REF_CTRL, SRCSEL, 0, 3)
 REG32(AFI3_REF_CTRL, 0x94)
-    FIELD(AFI3_REF_CTRL, CLKACT, 1, 24)
-    FIELD(AFI3_REF_CTRL, DIVISOR0, 6, 8)
-    FIELD(AFI3_REF_CTRL, SRCSEL, 3, 0)
+    FIELD(AFI3_REF_CTRL, CLKACT, 24, 1)
+    FIELD(AFI3_REF_CTRL, DIVISOR0, 8, 6)
+    FIELD(AFI3_REF_CTRL, SRCSEL, 0, 3)
 REG32(AFI4_REF_CTRL, 0x98)
-    FIELD(AFI4_REF_CTRL, CLKACT, 1, 24)
-    FIELD(AFI4_REF_CTRL, DIVISOR0, 6, 8)
-    FIELD(AFI4_REF_CTRL, SRCSEL, 3, 0)
+    FIELD(AFI4_REF_CTRL, CLKACT, 24, 1)
+    FIELD(AFI4_REF_CTRL, DIVISOR0, 8, 6)
+    FIELD(AFI4_REF_CTRL, SRCSEL, 0, 3)
 REG32(AFI5_REF_CTRL, 0x9c)
-    FIELD(AFI5_REF_CTRL, CLKACT, 1, 24)
-    FIELD(AFI5_REF_CTRL, DIVISOR0, 6, 8)
-    FIELD(AFI5_REF_CTRL, SRCSEL, 3, 0)
+    FIELD(AFI5_REF_CTRL, CLKACT, 24, 1)
+    FIELD(AFI5_REF_CTRL, DIVISOR0, 8, 6)
+    FIELD(AFI5_REF_CTRL, SRCSEL, 0, 3)
 REG32(SATA_REF_CTRL, 0xa0)
-    FIELD(SATA_REF_CTRL, CLKACT, 1, 24)
-    FIELD(SATA_REF_CTRL, DIVISOR0, 6, 8)
-    FIELD(SATA_REF_CTRL, SRCSEL, 3, 0)
+    FIELD(SATA_REF_CTRL, CLKACT, 24, 1)
+    FIELD(SATA_REF_CTRL, DIVISOR0, 8, 6)
+    FIELD(SATA_REF_CTRL, SRCSEL, 0, 3)
 REG32(PCIE_REF_CTRL, 0xb4)
-    FIELD(PCIE_REF_CTRL, CLKACT, 1, 24)
-    FIELD(PCIE_REF_CTRL, DIVISOR0, 6, 8)
-    FIELD(PCIE_REF_CTRL, SRCSEL, 3, 0)
+    FIELD(PCIE_REF_CTRL, CLKACT, 24, 1)
+    FIELD(PCIE_REF_CTRL, DIVISOR0, 8, 6)
+    FIELD(PCIE_REF_CTRL, SRCSEL, 0, 3)
 REG32(GDMA_REF_CTRL, 0xb8)
-    FIELD(GDMA_REF_CTRL, CLKACT, 1, 24)
-    FIELD(GDMA_REF_CTRL, DIVISOR0, 6, 8)
-    FIELD(GDMA_REF_CTRL, SRCSEL, 3, 0)
+    FIELD(GDMA_REF_CTRL, CLKACT, 24, 1)
+    FIELD(GDMA_REF_CTRL, DIVISOR0, 8, 6)
+    FIELD(GDMA_REF_CTRL, SRCSEL, 0, 3)
 REG32(DPDMA_REF_CTRL, 0xbc)
-    FIELD(DPDMA_REF_CTRL, CLKACT, 1, 24)
-    FIELD(DPDMA_REF_CTRL, DIVISOR0, 6, 8)
-    FIELD(DPDMA_REF_CTRL, SRCSEL, 3, 0)
+    FIELD(DPDMA_REF_CTRL, CLKACT, 24, 1)
+    FIELD(DPDMA_REF_CTRL, DIVISOR0, 8, 6)
+    FIELD(DPDMA_REF_CTRL, SRCSEL, 0, 3)
 REG32(TOPSW_MAIN_CTRL, 0xc0)
-    FIELD(TOPSW_MAIN_CTRL, CLKACT, 1, 24)
-    FIELD(TOPSW_MAIN_CTRL, DIVISOR0, 6, 8)
-    FIELD(TOPSW_MAIN_CTRL, SRCSEL, 3, 0)
+    FIELD(TOPSW_MAIN_CTRL, CLKACT, 24, 1)
+    FIELD(TOPSW_MAIN_CTRL, DIVISOR0, 8, 6)
+    FIELD(TOPSW_MAIN_CTRL, SRCSEL, 0, 3)
 REG32(TOPSW_LSBUS_CTRL, 0xc4)
-    FIELD(TOPSW_LSBUS_CTRL, CLKACT, 1, 24)
-    FIELD(TOPSW_LSBUS_CTRL, DIVISOR0, 6, 8)
-    FIELD(TOPSW_LSBUS_CTRL, SRCSEL, 3, 0)
+    FIELD(TOPSW_LSBUS_CTRL, CLKACT, 24, 1)
+    FIELD(TOPSW_LSBUS_CTRL, DIVISOR0, 8, 6)
+    FIELD(TOPSW_LSBUS_CTRL, SRCSEL, 0, 3)
 REG32(GTGREF0_REF_CTRL, 0xc8)
-    FIELD(GTGREF0_REF_CTRL, CLKACT, 1, 24)
-    FIELD(GTGREF0_REF_CTRL, DIVISOR0, 6, 8)
-    FIELD(GTGREF0_REF_CTRL, SRCSEL, 3, 0)
+    FIELD(GTGREF0_REF_CTRL, CLKACT, 24, 1)
+    FIELD(GTGREF0_REF_CTRL, DIVISOR0, 8, 6)
+    FIELD(GTGREF0_REF_CTRL, SRCSEL, 0, 3)
 REG32(GTGREF1_REF_CTRL, 0xcc)
-    FIELD(GTGREF1_REF_CTRL, CLKACT, 1, 24)
-    FIELD(GTGREF1_REF_CTRL, DIVISOR0, 6, 8)
-    FIELD(GTGREF1_REF_CTRL, SRCSEL, 3, 0)
+    FIELD(GTGREF1_REF_CTRL, CLKACT, 24, 1)
+    FIELD(GTGREF1_REF_CTRL, DIVISOR0, 8, 6)
+    FIELD(GTGREF1_REF_CTRL, SRCSEL, 0, 3)
 REG32(DFT300_REF_CTRL, 0xd0)
-    FIELD(DFT300_REF_CTRL, CLKACT, 1, 24)
-    FIELD(DFT300_REF_CTRL, DIVISOR0, 6, 8)
-    FIELD(DFT300_REF_CTRL, SRCSEL, 3, 0)
+    FIELD(DFT300_REF_CTRL, CLKACT, 24, 1)
+    FIELD(DFT300_REF_CTRL, DIVISOR0, 8, 6)
+    FIELD(DFT300_REF_CTRL, SRCSEL, 0, 3)
 REG32(DFT270_REF_CTRL, 0xd4)
-    FIELD(DFT270_REF_CTRL, CLKACT, 1, 24)
-    FIELD(DFT270_REF_CTRL, DIVISOR0, 6, 8)
-    FIELD(DFT270_REF_CTRL, SRCSEL, 3, 0)
+    FIELD(DFT270_REF_CTRL, CLKACT, 24, 1)
+    FIELD(DFT270_REF_CTRL, DIVISOR0, 8, 6)
+    FIELD(DFT270_REF_CTRL, SRCSEL, 0, 3)
 REG32(DFT250_REF_CTRL, 0xd8)
-    FIELD(DFT250_REF_CTRL, CLKACT, 1, 24)
-    FIELD(DFT250_REF_CTRL, DIVISOR0, 6, 8)
-    FIELD(DFT250_REF_CTRL, SRCSEL, 3, 0)
+    FIELD(DFT250_REF_CTRL, CLKACT, 24, 1)
+    FIELD(DFT250_REF_CTRL, DIVISOR0, 8, 6)
+    FIELD(DFT250_REF_CTRL, SRCSEL, 0, 3)
 REG32(DFT125_REF_CTRL, 0xdc)
-    FIELD(DFT125_REF_CTRL, CLKACT, 1, 24)
-    FIELD(DFT125_REF_CTRL, DIVISOR0, 6, 8)
-    FIELD(DFT125_REF_CTRL, SRCSEL, 3, 0)
+    FIELD(DFT125_REF_CTRL, CLKACT, 24, 1)
+    FIELD(DFT125_REF_CTRL, DIVISOR0, 8, 6)
+    FIELD(DFT125_REF_CTRL, SRCSEL, 0, 3)
 
 REG32(RST_FPD_TOP, 0x100)
-    FIELD(RST_FPD_TOP, PCIE_BRDG_RESET, 1, 18)
-    FIELD(RST_FPD_TOP, PCIE_CTRL_RESET, 1, 17)
-    FIELD(RST_FPD_TOP, DP_RESET, 1, 16)
-    FIELD(RST_FPD_TOP, AFI_FM5_RESET, 1, 12)
-    FIELD(RST_FPD_TOP, AFI_FM4_RESET, 1, 11)
-    FIELD(RST_FPD_TOP, AFI_FM3_RESET, 1, 10)
-    FIELD(RST_FPD_TOP, AFI_FM2_RESET, 1, 9)
-    FIELD(RST_FPD_TOP, AFI_FM1_RESET, 1, 8)
-    FIELD(RST_FPD_TOP, AFI_FM0_RESET, 1, 7)
-    FIELD(RST_FPD_TOP, GDMA_RESET, 1, 6)
-    FIELD(RST_FPD_TOP, GPU_PP1_RESET, 1, 5)
-    FIELD(RST_FPD_TOP, GPU_PP0_RESET, 1, 4)
-    FIELD(RST_FPD_TOP, GPU_RESET, 1, 3)
-    FIELD(RST_FPD_TOP, GT_RESET, 1, 2)
+    FIELD(RST_FPD_TOP, PCIE_BRDG_RESET, 18, 1)
+    FIELD(RST_FPD_TOP, PCIE_CTRL_RESET, 17, 1)
+    FIELD(RST_FPD_TOP, DP_RESET, 16, 1)
+    FIELD(RST_FPD_TOP, AFI_FM5_RESET, 12, 1)
+    FIELD(RST_FPD_TOP, AFI_FM4_RESET, 11, 1)
+    FIELD(RST_FPD_TOP, AFI_FM3_RESET, 10, 1)
+    FIELD(RST_FPD_TOP, AFI_FM2_RESET, 9, 1)
+    FIELD(RST_FPD_TOP, AFI_FM1_RESET, 8, 1)
+    FIELD(RST_FPD_TOP, AFI_FM0_RESET, 7, 1)
+    FIELD(RST_FPD_TOP, GDMA_RESET, 6, 1)
+    FIELD(RST_FPD_TOP, GPU_PP1_RESET, 5, 1)
+    FIELD(RST_FPD_TOP, GPU_PP0_RESET, 4, 1)
+    FIELD(RST_FPD_TOP, GPU_RESET, 3, 1)
+    FIELD(RST_FPD_TOP, GT_RESET, 2, 1)
     FIELD(RST_FPD_TOP, SATA_RESET, 1, 1)
 REG32(RST_FPD_APU, 0x104)
-    FIELD(RST_FPD_APU, PERI_RESET, 1, 13)
-    FIELD(RST_FPD_APU, SCU_RESET, 1, 12)
-    FIELD(RST_FPD_APU, CPU1_AWDT_RESET, 1, 9)
-    FIELD(RST_FPD_APU, CPU0_AWDT_RESET, 1, 8)
-    FIELD(RST_FPD_APU, CPU1_CP14_RESET, 1, 5)
-    FIELD(RST_FPD_APU, CPU0_CP14_RESET, 1, 4)
-    FIELD(RST_FPD_APU, CPU3_A9_RESET, 1, 3)
-    FIELD(RST_FPD_APU, CPU2_A9_RESET, 1, 2)
+    FIELD(RST_FPD_APU, PERI_RESET, 13, 1)
+    FIELD(RST_FPD_APU, SCU_RESET, 12, 1)
+    FIELD(RST_FPD_APU, CPU1_AWDT_RESET, 9, 1)
+    FIELD(RST_FPD_APU, CPU0_AWDT_RESET, 8, 1)
+    FIELD(RST_FPD_APU, CPU1_CP14_RESET, 5, 1)
+    FIELD(RST_FPD_APU, CPU0_CP14_RESET, 4, 1)
+    FIELD(RST_FPD_APU, CPU3_A9_RESET, 3, 1)
+    FIELD(RST_FPD_APU, CPU2_A9_RESET, 2, 1)
     FIELD(RST_FPD_APU, CPU1_A9_RESET, 1, 1)
-    FIELD(RST_FPD_APU, CPU0_A9_RESET, 1, 0)
+    FIELD(RST_FPD_APU, CPU0_A9_RESET, 0, 1)
 REG32(RST_DDR_SS, 0x108)
-    FIELD(RST_DDR_SS, DDR_RESET, 1, 3)
-    FIELD(RST_DDR_SS, APM_RESET, 1, 2)
+    FIELD(RST_DDR_SS, DDR_RESET, 3, 1)
+    FIELD(RST_DDR_SS, APM_RESET, 2, 1)
     FIELD(RST_DDR_SS, QOS_RESET, 1, 1)
-    FIELD(RST_DDR_SS, XMPU_RESET, 1, 0)
+    FIELD(RST_DDR_SS, XMPU_RESET, 0, 1)
 
 #define R_MAX (R_RST_DDR_SS + 1)
 
-- 
2.5.5