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[Qemu-devel] [PULL 30/30] target-arm: Don't permit ARMv8-only Neon insns
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 30/30] target-arm: Don't permit ARMv8-only Neon insns on ARMv7 |
Date: |
Tue, 14 Jun 2016 15:14:05 +0100 |
The Neon instructions VCVTA, VCVTM, VCVTN, VCVTP, VRINTA, VRINTM,
VRINTN, VRINTP, VRINTX, and VRINTZ were only introduced with ARMv8,
so they need a guard to make them UNDEF if the CPU only supports ARMv7.
(We got this right for all the other new-in-v8 insns, but forgot
it for these Neon 2-reg-misc ops.)
Reported-by: Christophe Lyon <address@hidden>
Tested-by: Christophe Lyon <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
---
target-arm/translate.c | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 6815bc1..3e71467 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -5311,6 +5311,30 @@ static int neon_2rm_is_float_op(int op)
op >= NEON_2RM_VRECPE_F);
}
+static bool neon_2rm_is_v8_op(int op)
+{
+ /* Return true if this neon 2reg-misc op is ARMv8 and up */
+ switch (op) {
+ case NEON_2RM_VRINTN:
+ case NEON_2RM_VRINTA:
+ case NEON_2RM_VRINTM:
+ case NEON_2RM_VRINTP:
+ case NEON_2RM_VRINTZ:
+ case NEON_2RM_VRINTX:
+ case NEON_2RM_VCVTAU:
+ case NEON_2RM_VCVTAS:
+ case NEON_2RM_VCVTNU:
+ case NEON_2RM_VCVTNS:
+ case NEON_2RM_VCVTPU:
+ case NEON_2RM_VCVTPS:
+ case NEON_2RM_VCVTMU:
+ case NEON_2RM_VCVTMS:
+ return true;
+ default:
+ return false;
+ }
+}
+
/* Each entry in this array has bit n set if the insn allows
* size value n (otherwise it will UNDEF). Since unallocated
* op values will have no bits set they always UNDEF.
@@ -6798,6 +6822,10 @@ static int disas_neon_data_insn(DisasContext *s,
uint32_t insn)
if ((neon_2rm_sizes[op] & (1 << size)) == 0) {
return 1;
}
+ if (neon_2rm_is_v8_op(op) &&
+ !arm_dc_feature(s, ARM_FEATURE_V8)) {
+ return 1;
+ }
if ((op != NEON_2RM_VMOVN && op != NEON_2RM_VQMOVN) &&
q && ((rm | rd) & 1)) {
return 1;
--
1.9.1
- [Qemu-devel] [PULL 15/30] hw/gpio: QOM'ify zaurus.c, (continued)
- [Qemu-devel] [PULL 15/30] hw/gpio: QOM'ify zaurus.c, Peter Maydell, 2016/06/14
- [Qemu-devel] [PULL 08/30] hw/arm/virt: create the 2.7 machine type, Peter Maydell, 2016/06/14
- [Qemu-devel] [PULL 10/30] hw/i2c: QOM'ify exynos4210_i2c.c, Peter Maydell, 2016/06/14
- [Qemu-devel] [PULL 11/30] hw/i2c: QOM'ify omap_i2c.c, Peter Maydell, 2016/06/14
- [Qemu-devel] [PULL 09/30] hw/i2c: QOM'ify bitbang_i2c.c, Peter Maydell, 2016/06/14
- [Qemu-devel] [PULL 18/30] hw/misc: QOM'ify mst_fpga.c, Peter Maydell, 2016/06/14
- [Qemu-devel] [PULL 17/30] hw/misc: QOM'ify exynos4210_pmu.c, Peter Maydell, 2016/06/14
- [Qemu-devel] [PULL 23/30] i2c: Factor our send() and recv() common logic, Peter Maydell, 2016/06/14
- [Qemu-devel] [PULL 22/30] i2c: implement broadcast write, Peter Maydell, 2016/06/14
- [Qemu-devel] [PULL 29/30] arm: xlnx-zynqmp: Add xlnx-dp and xlnx-dpdma, Peter Maydell, 2016/06/14
- [Qemu-devel] [PULL 30/30] target-arm: Don't permit ARMv8-only Neon insns on ARMv7,
Peter Maydell <=
- [Qemu-devel] [PULL 21/30] i2cbus: remove unused dev field, Peter Maydell, 2016/06/14
- [Qemu-devel] [PULL 20/30] hw/sd: QOM'ify pl181.c, Peter Maydell, 2016/06/14
- [Qemu-devel] [PULL 24/30] introduce aux-bus, Peter Maydell, 2016/06/14
- [Qemu-devel] [PULL 03/30] hw/arm/virt-acpi-build: Add PMU IRQ number in ACPI table, Peter Maydell, 2016/06/14
- [Qemu-devel] [PULL 27/30] introduce xlnx-dpdma, Peter Maydell, 2016/06/14
- [Qemu-devel] [PULL 07/30] hw/arm/virt: introduce DEFINE_VIRT_MACHINE_AS_LATEST, Peter Maydell, 2016/06/14
- [Qemu-devel] [PULL 19/30] hw/dma: QOM'ify pxa2xx_dma.c, Peter Maydell, 2016/06/14
- [Qemu-devel] [PULL 25/30] introduce dpcd module, Peter Maydell, 2016/06/14
- [Qemu-devel] [PULL 26/30] hw/i2c-ddc.c: Implement DDC I2C slave, Peter Maydell, 2016/06/14
- [Qemu-devel] [PULL 28/30] introduce xlnx-dp, Peter Maydell, 2016/06/14