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[Qemu-devel] [PATCH v3 00/20] GICv3 emulation
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH v3 00/20] GICv3 emulation |
Date: |
Tue, 14 Jun 2016 15:38:12 +0100 |
This series implements emulation of the GICv3 interrupt controller.
It is based to some extent on previous patches from Shlomo and
Pavel, but the bulk of it has turned out to be new code. (The
combination of changing the underlying data structures, adding
support for TrustZone and implementing proper GICv3 behaviour rather
than borrowing fragments of GICv2 emulation code meant there wasn't
much left to reuse.) I've tried to reflect this in the various
authorship credits on the patches, but please let me know if you
feel I got anything miscredited one way or the other.
Key points about the GICv3 emulated here:
* "non-legacy" only, ie system registers and affinity routing
* TrustZone is implemented
* no virtualization support
* only the "core" GICv3, so no LPI support (via ITS or otherwise)
* no attempt to work around the Linux guest kernel bug fixed
in commit 7c9b973061b0 (so you need that fix for your guest to
boot with this GICv3)
Changes v2->v3: (all pretty minor)
* add missing blank lines in tests/test-bitops.c
* fixed erroneous comment
* fixed missing shift in gicv3_cache_target_cpustate()
* tweaked assertion in gicv3_set_irq()
* corrected condition governing when GICD_NSACR and GICR_NSACR are RAZ/WI
* dropped the RFC KVM save/restore patches for now
(they wouldn't have changed and aren't going to get into QEMU 2.7
since the kernel side of the interface is not going to hit the
kernel's merge window; will pick them back up later)
The following patches are the only ones that still need review:
08 hw/intc/arm_gicv3: Add vmstate descriptors
10 hw/intc/arm_gicv3: Implement functions to identify next pending irq
11 hw/intc/arm_gicv3: Implement GICv3 distributor registers
12 hw/intc/arm_gicv3: Implement GICv3 redistributor registers
15 hw/intc/arm_gicv3: Implement GICv3 CPU interface registers
16 hw/intc/arm_gicv3: Implement gicv3_cpuif_update()
18 hw/intc/arm_gicv3: Add IRQ handling CPU interface registers
thanks
-- PMM
Pavel Fedin (3):
target-arm: Add mp-affinity property for ARM CPU class
hw/intc/arm_gicv3: Add state information
hw/intc/arm_gicv3: Add vmstate descriptors
Peter Maydell (14):
migration: Define VMSTATE_UINT64_2DARRAY
bitops.h: Implement half-shuffle and half-unshuffle ops
target-arm: Define new arm_is_el3_or_mon() function
target-arm: Provide hook to tell GICv3 about changes of security state
hw/intc/arm_gicv3: Move irq lines into GICv3CPUState structure
hw/intc/arm_gicv3: Implement functions to identify next pending irq
hw/intc/arm_gicv3: Wire up distributor and redistributor MMIO regions
hw/intc/arm_gicv3: Implement gicv3_set_irq()
hw/intc/arm_gicv3: Implement GICv3 CPU interface registers
hw/intc/arm_gicv3: Implement gicv3_cpuif_update()
hw/intc/arm_gicv3: Implement CPU i/f SGI generation registers
hw/intc/arm_gicv3: Add IRQ handling CPU interface registers
target-arm/machine.c: Allow user to request GICv3 emulation
target-arm/monitor.c: Advertise emulated GICv3 in capabilities
Shlomo Pongratz (3):
hw/intc/arm_gicv3: ARM GICv3 device framework
hw/intc/arm_gicv3: Implement GICv3 distributor registers
hw/intc/arm_gicv3: Implement GICv3 redistributor registers
hw/intc/Makefile.objs | 4 +
hw/intc/arm_gicv3.c | 400 +++++++++++
hw/intc/arm_gicv3_common.c | 225 +++++-
hw/intc/arm_gicv3_cpuif.c | 1346 ++++++++++++++++++++++++++++++++++++
hw/intc/arm_gicv3_dist.c | 879 +++++++++++++++++++++++
hw/intc/arm_gicv3_kvm.c | 7 +
hw/intc/arm_gicv3_redist.c | 562 +++++++++++++++
hw/intc/gicv3_internal.h | 331 +++++++++
include/hw/intc/arm_gicv3.h | 32 +
include/hw/intc/arm_gicv3_common.h | 215 +++++-
include/migration/vmstate.h | 6 +
include/qemu/bitops.h | 108 +++
target-arm/cpu.c | 10 +
target-arm/cpu.h | 47 +-
target-arm/helper.c | 2 +
target-arm/internals.h | 8 +
target-arm/machine.c | 3 +-
target-arm/monitor.c | 3 +-
target-arm/op_helper.c | 4 +
tests/test-bitops.c | 72 ++
trace-events | 41 ++
21 files changed, 4285 insertions(+), 20 deletions(-)
create mode 100644 hw/intc/arm_gicv3.c
create mode 100644 hw/intc/arm_gicv3_cpuif.c
create mode 100644 hw/intc/arm_gicv3_dist.c
create mode 100644 hw/intc/arm_gicv3_redist.c
create mode 100644 hw/intc/gicv3_internal.h
create mode 100644 include/hw/intc/arm_gicv3.h
--
1.9.1
- [Qemu-devel] [PATCH v3 00/20] GICv3 emulation,
Peter Maydell <=
- [Qemu-devel] [PATCH v3 02/20] bitops.h: Implement half-shuffle and half-unshuffle ops, Peter Maydell, 2016/06/14
- [Qemu-devel] [PATCH v3 17/20] hw/intc/arm_gicv3: Implement CPU i/f SGI generation registers, Peter Maydell, 2016/06/14
- [Qemu-devel] [PATCH v3 19/20] target-arm/machine.c: Allow user to request GICv3 emulation, Peter Maydell, 2016/06/14
- [Qemu-devel] [PATCH v3 16/20] hw/intc/arm_gicv3: Implement gicv3_cpuif_update(), Peter Maydell, 2016/06/14
- [Qemu-devel] [PATCH v3 15/20] hw/intc/arm_gicv3: Implement GICv3 CPU interface registers, Peter Maydell, 2016/06/14
- [Qemu-devel] [PATCH v3 01/20] migration: Define VMSTATE_UINT64_2DARRAY, Peter Maydell, 2016/06/14
- [Qemu-devel] [PATCH v3 10/20] hw/intc/arm_gicv3: Implement functions to identify next pending irq, Peter Maydell, 2016/06/14