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[Qemu-devel] [PATCH v3 03/20] target-arm: Define new arm_is_el3_or_mon()
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH v3 03/20] target-arm: Define new arm_is_el3_or_mon() function |
Date: |
Tue, 14 Jun 2016 15:38:15 +0100 |
The GICv3 system registers need to know if the CPU is AArch64
in EL3 or AArch32 in Monitor mode. This happens to be the first
part of the check for arm_is_secure(), so factor it out into a
new arm_is_el3_or_mon() function that the GIC can also use.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Shannon Zhao <address@hidden>
---
target-arm/cpu.h | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 17d8051..2c2b8f7 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -1144,8 +1144,8 @@ static inline bool arm_is_secure_below_el3(CPUARMState
*env)
}
}
-/* Return true if the processor is in secure state */
-static inline bool arm_is_secure(CPUARMState *env)
+/* Return true if the CPU is AArch64 EL3 or AArch32 Mon */
+static inline bool arm_is_el3_or_mon(CPUARMState *env)
{
if (arm_feature(env, ARM_FEATURE_EL3)) {
if (is_a64(env) && extract32(env->pstate, 2, 2) == 3) {
@@ -1157,6 +1157,15 @@ static inline bool arm_is_secure(CPUARMState *env)
return true;
}
}
+ return false;
+}
+
+/* Return true if the processor is in secure state */
+static inline bool arm_is_secure(CPUARMState *env)
+{
+ if (arm_is_el3_or_mon(env)) {
+ return true;
+ }
return arm_is_secure_below_el3(env);
}
--
1.9.1
- [Qemu-devel] [PATCH v3 15/20] hw/intc/arm_gicv3: Implement GICv3 CPU interface registers, (continued)
- [Qemu-devel] [PATCH v3 15/20] hw/intc/arm_gicv3: Implement GICv3 CPU interface registers, Peter Maydell, 2016/06/14
- [Qemu-devel] [PATCH v3 01/20] migration: Define VMSTATE_UINT64_2DARRAY, Peter Maydell, 2016/06/14
- [Qemu-devel] [PATCH v3 10/20] hw/intc/arm_gicv3: Implement functions to identify next pending irq, Peter Maydell, 2016/06/14
- [Qemu-devel] [PATCH v3 04/20] target-arm: Provide hook to tell GICv3 about changes of security state, Peter Maydell, 2016/06/14
- [Qemu-devel] [PATCH v3 14/20] hw/intc/arm_gicv3: Implement gicv3_set_irq(), Peter Maydell, 2016/06/14
- [Qemu-devel] [PATCH v3 09/20] hw/intc/arm_gicv3: ARM GICv3 device framework, Peter Maydell, 2016/06/14
- [Qemu-devel] [PATCH v3 05/20] target-arm: Add mp-affinity property for ARM CPU class, Peter Maydell, 2016/06/14
- [Qemu-devel] [PATCH v3 07/20] hw/intc/arm_gicv3: Move irq lines into GICv3CPUState structure, Peter Maydell, 2016/06/14
- [Qemu-devel] [PATCH v3 03/20] target-arm: Define new arm_is_el3_or_mon() function,
Peter Maydell <=
- [Qemu-devel] [PATCH v3 08/20] hw/intc/arm_gicv3: Add vmstate descriptors, Peter Maydell, 2016/06/14
- [Qemu-devel] [PATCH v3 12/20] hw/intc/arm_gicv3: Implement GICv3 redistributor registers, Peter Maydell, 2016/06/14
- [Qemu-devel] [PATCH v3 06/20] hw/intc/arm_gicv3: Add state information, Peter Maydell, 2016/06/14
- [Qemu-devel] [PATCH v3 11/20] hw/intc/arm_gicv3: Implement GICv3 distributor registers, Peter Maydell, 2016/06/14
- [Qemu-devel] [PATCH v3 13/20] hw/intc/arm_gicv3: Wire up distributor and redistributor MMIO regions, Peter Maydell, 2016/06/14