[Qemu-devel] [PATCH v7 12/12] target-avr: 1. use cpu_get/set_sreg function at avr_cpu_gdb_read_register/avr_cpu_gdb_read_register 2. configuring target as little endian 3. fixing and testing gen_push_ret/gen_pop_ret

[Michael Rolnik]

Signed-off-by: Michael Rolnik <address@hidden>
---
 configure                   |  2 +-
 target-avr/gdbstub.c        | 19 ++-----------------
 target-avr/translate-inst.c | 45 +++++++++++++++++++++++++--------------------
 target-avr/translate.c      |  5 -----
 4 files changed, 28 insertions(+), 43 deletions(-)

diff --git a/configure b/configure
index 41e550e..a925b4b 100755
--- a/configure
+++ b/configure
@@ -5603,7 +5603,7 @@ target_name=$(echo $target | cut -d '-' -f 1)
 target_bigendian="no"
 
 case "$target_name" in
-  
avr|armeb|lm32|m68k|microblaze|mips|mipsn32|mips64|moxie|or32|ppc|ppcemb|ppc64|ppc64abi32|s390x|sh4eb|sparc|sparc64|sparc32plus|xtensaeb)
+  
armeb|lm32|m68k|microblaze|mips|mipsn32|mips64|moxie|or32|ppc|ppcemb|ppc64|ppc64abi32|s390x|sh4eb|sparc|sparc64|sparc32plus|xtensaeb)
   target_bigendian=yes
   ;;
 esac
diff --git a/target-avr/gdbstub.c b/target-avr/gdbstub.c
index d9a3666..a53ba09 100644
--- a/target-avr/gdbstub.c
+++ b/target-avr/gdbstub.c
@@ -34,16 +34,8 @@ int avr_cpu_gdb_read_register(CPUState *cs, uint8_t 
*mem_buf, int n)
 
     /*  SREG */
     if (n == 32) {
-        uint8_t sreg = 0;
+        uint8_t sreg = cpu_get_sreg(env);
 
-        sreg =   (env->sregC & 0x01) << 0
-                |   (env->sregZ & 0x01) << 1
-                |   (env->sregN & 0x01) << 2
-                |   (env->sregV & 0x01) << 3
-                |   (env->sregS & 0x01) << 4
-                |   (env->sregH & 0x01) << 5
-                |   (env->sregT & 0x01) << 6
-                |   (env->sregI & 0x01) << 7;
         return gdb_get_reg8(mem_buf, sreg);
     }
 
@@ -73,14 +65,7 @@ int avr_cpu_gdb_write_register(CPUState *cs, uint8_t 
*mem_buf, int n)
 
     /*  SREG */
     if (n == 32) {
-        env->sregC = (tmp >> 0) & 0x01;
-        env->sregZ = (tmp >> 1) & 0x01;
-        env->sregN = (tmp >> 2) & 0x01;
-        env->sregV = (tmp >> 3) & 0x01;
-        env->sregS = (tmp >> 4) & 0x01;
-        env->sregH = (tmp >> 5) & 0x01;
-        env->sregT = (tmp >> 6) & 0x01;
-        env->sregI = (tmp >> 7) & 0x01;
+        cpu_set_sreg(env, tmp);
     }
 
     /*  SP */
diff --git a/target-avr/translate-inst.c b/target-avr/translate-inst.c
index 2868672..280705b 100644
--- a/target-avr/translate-inst.c
+++ b/target-avr/translate-inst.c
@@ -136,7 +136,7 @@ void gen_push_ret(CPUAVRState *env, int ret)
 
         TCGv t0 = tcg_const_i32((ret & 0x0000ff));
 
-        tcg_gen_qemu_st8(t0, cpu_sp, MMU_DATA_IDX);
+        tcg_gen_qemu_st_tl(t0, cpu_sp, MMU_DATA_IDX, MO_UB);
         tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);
 
         tcg_temp_free_i32(t0);
@@ -144,23 +144,24 @@ void gen_push_ret(CPUAVRState *env, int ret)
 
         TCGv t0 = tcg_const_i32((ret & 0x00ffff));
 
-        tcg_gen_qemu_st16(t0, cpu_sp, MMU_DATA_IDX);
-        tcg_gen_subi_tl(cpu_sp, cpu_sp, 2);
+        tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);
+        tcg_gen_qemu_st_tl(t0, cpu_sp, MMU_DATA_IDX, MO_BEUW);
+        tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);
 
         tcg_temp_free_i32(t0);
-    } else if (avr_feature(env, AVR_FEATURE_3_BYTE_PC)) {
 
-        TCGv t0 = tcg_const_i32((ret & 0x0000ff));
-        TCGv t1 = tcg_const_i32((ret & 0xffff00) >> 8);
+    } else if (avr_feature(env, AVR_FEATURE_3_BYTE_PC)) {
 
-        tcg_gen_qemu_st8(t0, cpu_sp, MMU_DATA_IDX);
-        tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);
+        TCGv lo = tcg_const_i32((ret & 0x0000ff));
+        TCGv hi = tcg_const_i32((ret & 0xffff00) >> 8);
 
-        tcg_gen_qemu_st16(t1, cpu_sp, MMU_DATA_IDX);
+        tcg_gen_qemu_st_tl(lo, cpu_sp, MMU_DATA_IDX, MO_UB);
         tcg_gen_subi_tl(cpu_sp, cpu_sp, 2);
+        tcg_gen_qemu_st_tl(hi, cpu_sp, MMU_DATA_IDX, MO_BEUW);
+        tcg_gen_subi_tl(cpu_sp, cpu_sp, 1);
 
-        tcg_temp_free_i32(t0);
-        tcg_temp_free_i32(t1);
+        tcg_temp_free_i32(lo);
+        tcg_temp_free_i32(hi);
     }
 }
 
@@ -169,25 +170,29 @@ void gen_pop_ret(CPUAVRState *env, TCGv ret)
     if (avr_feature(env, AVR_FEATURE_1_BYTE_PC)) {
 
         tcg_gen_addi_tl(cpu_sp, cpu_sp, 1);
-        tcg_gen_qemu_ld8u(ret, cpu_sp, MMU_DATA_IDX);
+        tcg_gen_qemu_ld_tl(ret, cpu_sp, MMU_DATA_IDX, MO_UB);
+
     } else if (avr_feature(env, AVR_FEATURE_2_BYTE_PC)) {
 
-        tcg_gen_addi_tl(cpu_sp, cpu_sp, 2);
-        tcg_gen_qemu_ld16u(ret, cpu_sp, MMU_DATA_IDX);
+        tcg_gen_addi_tl(cpu_sp, cpu_sp, 1);
+        tcg_gen_qemu_ld_tl(ret, cpu_sp, MMU_DATA_IDX, MO_BEUW);
+        tcg_gen_addi_tl(cpu_sp, cpu_sp, 1);
+
     } else if (avr_feature(env, AVR_FEATURE_3_BYTE_PC)) {
 
-        TCGv t0 = tcg_temp_new_i32();
+        TCGv lo = tcg_temp_new_i32();
+        TCGv hi = tcg_temp_new_i32();
 
         tcg_gen_addi_tl(cpu_sp, cpu_sp, 1);
-        tcg_gen_qemu_ld8u(ret, cpu_sp, MMU_DATA_IDX);
+        tcg_gen_qemu_ld_tl(hi, cpu_sp, MMU_DATA_IDX, MO_BEUW);
 
         tcg_gen_addi_tl(cpu_sp, cpu_sp, 2);
-        tcg_gen_qemu_ld16u(t0, cpu_sp, MMU_DATA_IDX);
+        tcg_gen_qemu_ld_tl(lo, cpu_sp, MMU_DATA_IDX, MO_UB);
 
-        tcg_gen_shli_tl(t0, t0, 16);
-        tcg_gen_or_tl(ret, ret, t0);
+        tcg_gen_deposit_tl(ret, lo, hi, 8, 16);
 
-        tcg_temp_free_i32(t0);
+        tcg_temp_free_i32(lo);
+        tcg_temp_free_i32(hi);
     }
 }
 
diff --git a/target-avr/translate.c b/target-avr/translate.c
index 28babc9..146d43a 100644
--- a/target-avr/translate.c
+++ b/target-avr/translate.c
@@ -95,11 +95,6 @@ static void decode_opc(AVRCPU *cpu, DisasContext *ctx, 
InstInfo *inst)
     CPUAVRState        *env = &cpu->env;
 
     inst->opcode = cpu_ldl_code(env, inst->cpc * 2);/*  pc points to words  */
-        /*  target is defined as bigendian for push_ret/pop_ret
-            optimization. but my decode assumes instruction to be in little
-            endian format, hence bswap
-        */
-    inst->opcode = bswap32(inst->opcode);
     inst->length = 16;
     inst->translate = NULL;
 
-- 
2.4.9 (Apple Git-60)