Re: [Qemu-devel] [RFC v3 PATCH 02/14] tcg/i386: Add support for fence

[Alex Bennée]

Richard Henderson <address@hidden> writes:

> On 06/22/2016 09:25 AM, Alex Bennée wrote:
>>
>> Pranith Kumar <address@hidden> writes:
>>
>>> Generate mfence/sfence/lfence instruction on SSE2 enabled
>>> processors. For older processors, generate a 'lock orl $0,0(%esp)'
>>> instruction which has full ordering semantics.
>>>
>>> Signed-off-by: Pranith Kumar <address@hidden>
>>> [rth: Check for sse2, fallback to locked memory op otherwise.]
>>> Signed-off-by: Richard Henderson <address@hidden>
>>> ---
>>>  tcg/i386/tcg-target.inc.c | 47 
>>> +++++++++++++++++++++++++++++++++++++++++++++++
>>>  1 file changed, 47 insertions(+)
>>>
>>> diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
>>> index 317484c..0748652 100644
>>> --- a/tcg/i386/tcg-target.inc.c
>>> +++ b/tcg/i386/tcg-target.inc.c
>>> @@ -121,6 +121,16 @@ static bool have_cmov;
>>>  # define have_cmov 0
>>>  #endif
>>>
>>> +/* For 32-bit, we are going to attempt to determine at runtime whether
>>> +   sse2 support is available.  */
>>> +#if TCG_TARGET_REG_BITS == 64 || defined(__SSE2__)
>>
>> Hmm checkpatch.pl warns against including architecture specific defines.
>> Is the || leg only going to trigger when building 32 bit x86 with custom
>> compiler flags to force SSE2 code?
>
> Yes, e.g. -march=native.
>
> I think checkpatch should be ignored in this situation.  There's precedent
> elsewhere in the tcg backends.  And it's definitely architecture specific 
> code.
>  ;-)

Fair enough, I bow to your maintainerly view ;-)

--
Alex Bennée