Re: [Qemu-devel] [V12 4/4] hw/i386: AMD IOMMU IVRS table

[Jan Kiszka]

On 2016-06-15 14:21, David Kiarie wrote:
> Add IVRS table for AMD IOMMU. Generate IVRS or DMAR
> depending on emulated IOMMU.
> 
> Signed-off-by: David Kiarie <address@hidden>
> ---
>  hw/acpi/aml-build.c         |  2 +-
>  hw/i386/acpi-build.c        | 95 
> +++++++++++++++++++++++++++++++++++++++------
>  include/hw/acpi/acpi-defs.h | 13 +++++++
>  include/hw/acpi/aml-build.h |  1 +
>  4 files changed, 99 insertions(+), 12 deletions(-)
> 
> diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
> index 123160a..9ce10aa 100644
> --- a/hw/acpi/aml-build.c
> +++ b/hw/acpi/aml-build.c
> @@ -226,7 +226,7 @@ static void build_extop_package(GArray *package, uint8_t 
> op)
>      build_prepend_byte(package, 0x5B); /* ExtOpPrefix */
>  }
>  
> -static void build_append_int_noprefix(GArray *table, uint64_t value, int 
> size)
> +void build_append_int_noprefix(GArray *table, uint64_t value, int size)
>  {
>      int i;
>  
> diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
> index 8ca2032..ecdb15d 100644
> --- a/hw/i386/acpi-build.c
> +++ b/hw/i386/acpi-build.c
> @@ -51,6 +51,7 @@
>  #include "hw/pci/pci_bus.h"
>  #include "hw/pci-host/q35.h"
>  #include "hw/i386/intel_iommu.h"
> +#include "hw/i386/amd_iommu.h"
>  #include "hw/timer/hpet.h"
>  
>  #include "hw/acpi/aml-build.h"
> @@ -116,6 +117,12 @@ typedef struct AcpiBuildPciBusHotplugState {
>      bool pcihp_bridge_en;
>  } AcpiBuildPciBusHotplugState;
>  
> +typedef enum IommuType {
> +    TYPE_INTEL,
> +    TYPE_AMD,
> +    TYPE_NONE
> +} IommuType;
> +
>  static void acpi_get_pm_info(AcpiPmInfo *pm)
>  {
>      Object *piix = piix4_pm_find();
> @@ -2439,6 +2446,77 @@ build_dmar_q35(GArray *table_data, BIOSLinker *linker)
>                   "DMAR", table_data->len - dmar_start, 1, NULL, NULL);
>  }
>  
> +static void
> +build_amd_iommu(GArray *table_data, BIOSLinker *linker)
> +{
> +    int iommu_start = table_data->len;
> +    bool iommu_ambig;
> +
> +    /* IVRS definition  - table header has an extra 2-byte field */
> +    acpi_data_push(table_data, sizeof(AcpiTableHeader));
> +    /* common virtualization information */
> +    build_append_int_noprefix(table_data, AMD_IOMMU_HOST_ADDRESS_WIDTH << 8, 
> 4);
> +    /* reserved */
> +    build_append_int_noprefix(table_data, 0, 8);
> +
> +    AMDVIState *s = (AMDVIState *)object_resolve_path_type("",
> +                        TYPE_AMD_IOMMU_DEVICE, &iommu_ambig);
> +
> +    /* IVDB definition - type 10h */
> +    if (!iommu_ambig) {
> +        /* IVHD definition - type 10h */
> +        build_append_int_noprefix(table_data, 0x10, 1);
> +        /* virtualization flags */
> +        build_append_int_noprefix(table_data, (IVHD_HT_TUNEN |
> +                     IVHD_PPRSUP | IVHD_IOTLBSUP | IVHD_PREFSUP), 1);
> +        /* ivhd length */
> +        build_append_int_noprefix(table_data, 0x20, 2);
> +        /* iommu device id */
> +        build_append_int_noprefix(table_data, s->devid, 2);
> +        /* offset of capability registers */
> +        build_append_int_noprefix(table_data, s->capab_offset, 2);
> +        /* mmio base register */
> +        build_append_int_noprefix(table_data, s->mmio.addr, 8);
> +        /* pci segment */
> +        build_append_int_noprefix(table_data, 0, 2);
> +        /* interrupt numbers */
> +        build_append_int_noprefix(table_data, 0, 2);
> +        /* feature reporting */
> +        build_append_int_noprefix(table_data, (IVHD_EFR_GTSUP |
> +                    IVHD_EFR_HATS | IVHD_EFR_GATS), 4);
> +        /* Add device flags here
> +         *   These are 4-byte device entries currently reporting the range of
> +         *   devices 00h - ffffh; all devices
> +         *   Device setting affecting all devices should be made here
> +         *
> +         *   Refer to
> +         *   (http://support.amd.com/TechDocs/48882_IOMMU.pdf)
> +         *   Table 95
> +         */
> +        /* start of device range, 4-byte entries */
> +        build_append_int_noprefix(table_data, 0x00000003, 4);
> +        /* end of device range */
> +        build_append_int_noprefix(table_data, 0x00ffff04, 4);
> +    }
> +
> +    build_header(linker, table_data, (void *)(table_data->data + 
> iommu_start),
> +                 "IVRS", table_data->len - iommu_start, 1, NULL, NULL);
> +}
> +
> +static IommuType has_iommu(void)
> +{
> +    bool ambiguous;
> +
> +    if (object_resolve_path_type("", TYPE_AMD_IOMMU_DEVICE, &ambiguous)
> +            && !ambiguous)
> +        return TYPE_AMD;
> +    else if (object_resolve_path_type("", TYPE_INTEL_IOMMU_DEVICE, 
> &ambiguous)
> +            && !ambiguous)
> +        return TYPE_INTEL;
> +    else
> +        return TYPE_NONE;

Style: { }

Jan

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