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[Qemu-devel] [PULL 14/17] ppc: Turn a bunch of booleans from int to bool
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 14/17] ppc: Turn a bunch of booleans from int to bool |
Date: |
Thu, 23 Jun 2016 15:48:43 +1000 |
From: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target-ppc/translate.c | 37 ++++++++++++++++++-------------------
1 file changed, 18 insertions(+), 19 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 2bbe210..55102bf 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -193,22 +193,21 @@ struct DisasContext {
uint32_t opcode;
uint32_t exception;
/* Routine used to access memory */
- bool pr, hv, dr;
+ bool pr, hv, dr, le_mode;
bool lazy_tlb_flush;
int mem_idx;
int access_type;
/* Translation flags */
- int le_mode;
TCGMemOp default_tcg_memop_mask;
#if defined(TARGET_PPC64)
- int sf_mode;
- int has_cfar;
+ bool sf_mode;
+ bool has_cfar;
#endif
- int fpu_enabled;
- int altivec_enabled;
- int vsx_enabled;
- int spe_enabled;
- int tm_enabled;
+ bool fpu_enabled;
+ bool altivec_enabled;
+ bool vsx_enabled;
+ bool spe_enabled;
+ bool tm_enabled;
ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
int singlestep_enabled;
uint64_t insns_flags;
@@ -11496,7 +11495,7 @@ void gen_intermediate_code(CPUPPCState *env, struct
TranslationBlock *tb)
ctx.insns_flags = env->insns_flags;
ctx.insns_flags2 = env->insns_flags2;
ctx.access_type = -1;
- ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
+ ctx.le_mode = !!(env->hflags & (1 << MSR_LE));
ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE;
#if defined(TARGET_PPC64)
ctx.sf_mode = msr_is_64bit(env, env->msr);
@@ -11507,25 +11506,25 @@ void gen_intermediate_code(CPUPPCState *env, struct
TranslationBlock *tb)
(env->mmu_model & POWERPC_MMU_64B))
ctx.lazy_tlb_flush = true;
- ctx.fpu_enabled = msr_fp;
+ ctx.fpu_enabled = !!msr_fp;
if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
- ctx.spe_enabled = msr_spe;
+ ctx.spe_enabled = !!msr_spe;
else
- ctx.spe_enabled = 0;
+ ctx.spe_enabled = false;
if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
- ctx.altivec_enabled = msr_vr;
+ ctx.altivec_enabled = !!msr_vr;
else
- ctx.altivec_enabled = 0;
+ ctx.altivec_enabled = false;
if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
- ctx.vsx_enabled = msr_vsx;
+ ctx.vsx_enabled = !!msr_vsx;
} else {
- ctx.vsx_enabled = 0;
+ ctx.vsx_enabled = false;
}
#if defined(TARGET_PPC64)
if ((env->flags & POWERPC_FLAG_TM) && msr_tm) {
- ctx.tm_enabled = msr_tm;
+ ctx.tm_enabled = !!msr_tm;
} else {
- ctx.tm_enabled = 0;
+ ctx.tm_enabled = false;
}
#endif
if ((env->flags & POWERPC_FLAG_SE) && msr_se)
--
2.5.5
- [Qemu-devel] [PULL 00/17] ppc-for-2.7 queue 20160623, David Gibson, 2016/06/23
- [Qemu-devel] [PULL 02/17] tests: Use '+=' to add additional tests, not '=', David Gibson, 2016/06/23
- [Qemu-devel] [PULL 01/17] powerpc/mm: Update the WIMG check during H_ENTER, David Gibson, 2016/06/23
- [Qemu-devel] [PULL 06/17] memory: Add reporting of supported page sizes, David Gibson, 2016/06/23
- [Qemu-devel] [PULL 17/17] ppc: Disable huge page support if it is not available for main RAM, David Gibson, 2016/06/23
- [Qemu-devel] [PULL 03/17] ppc64: disable gen_pause() for linux-user mode, David Gibson, 2016/06/23
- [Qemu-devel] [PULL 07/17] ppc: Fix rfi/rfid/hrfi/... emulation, David Gibson, 2016/06/23
- [Qemu-devel] [PULL 09/17] ppc: fix exception model for HV mode, David Gibson, 2016/06/23
- [Qemu-devel] [PULL 05/17] ppc: Improve emulation of THRM registers, David Gibson, 2016/06/23
- [Qemu-devel] [PULL 11/17] ppc: Fix generation if ISI/DSI vs. HV mode, David Gibson, 2016/06/23
- [Qemu-devel] [PULL 14/17] ppc: Turn a bunch of booleans from int to bool,
David Gibson <=
- [Qemu-devel] [PULL 08/17] ppc: define a default LPCR value, David Gibson, 2016/06/23
- [Qemu-devel] [PULL 15/17] ppc: Move exception generation code out of line, David Gibson, 2016/06/23
- [Qemu-devel] [PULL 12/17] ppc: Rework generation of priv and inval interrupts, David Gibson, 2016/06/23
- [Qemu-devel] [PULL 10/17] ppc: Fix POWER7 and POWER8 exception definitions, David Gibson, 2016/06/23
- [Qemu-devel] [PULL 16/17] ppc: Add P7/P8 Power Management instructions, David Gibson, 2016/06/23
- [Qemu-devel] [PULL 13/17] ppc: Add real mode CI load/store instructions for P7 and P8, David Gibson, 2016/06/23
- [Qemu-devel] [PULL 04/17] target-ppc: Fix rlwimi, rlwinm, rlwnm again, David Gibson, 2016/06/23
- Re: [Qemu-devel] [PULL 00/17] ppc-for-2.7 queue 20160623, Peter Maydell, 2016/06/23