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[Qemu-devel] [PULL 08/17] ppc: define a default LPCR value
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 08/17] ppc: define a default LPCR value |
Date: |
Thu, 23 Jun 2016 15:48:37 +1000 |
From: Benjamin Herrenschmidt <address@hidden>
This allows us to set the appropriate LPCR bits which will be used
when fixing the exception model for the HV mode.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Reviewed-by: David Gibson <address@hidden>
[clg: previous commit 26a7f1291bb5 did not include the LPCR setting as
it was not needed at the time, adapted commit log ]
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target-ppc/translate_init.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index c847a3e..db56a39 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8518,6 +8518,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
void cpu_ppc_set_papr(PowerPCCPU *cpu)
{
CPUPPCState *env = &cpu->env;
+ ppc_spr_t *lpcr = &env->spr_cb[SPR_LPCR];
ppc_spr_t *amor = &env->spr_cb[SPR_AMOR];
/* PAPR always has exception vectors in RAM not ROM. To ensure this,
@@ -8527,6 +8528,19 @@ void cpu_ppc_set_papr(PowerPCCPU *cpu)
*/
env->msr_mask &= ~((1ull << MSR_EP) | MSR_HVB);
+ /* Set emulated LPCR to not send interrupts to hypervisor. Note that
+ * under KVM, the actual HW LPCR will be set differently by KVM itself,
+ * the settings below ensure proper operations with TCG in absence of
+ * a real hypervisor
+ */
+ lpcr->default_value &= ~(LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV);
+ lpcr->default_value |= LPCR_LPES0 | LPCR_LPES1;
+
+ /* We should be followed by a CPU reset but update the active value
+ * just in case...
+ */
+ env->spr[SPR_LPCR] = lpcr->default_value;
+
/* Set a full AMOR so guest can use the AMR as it sees fit */
env->spr[SPR_AMOR] = amor->default_value = 0xffffffffffffffffull;
--
2.5.5
- [Qemu-devel] [PULL 02/17] tests: Use '+=' to add additional tests, not '=', (continued)
- [Qemu-devel] [PULL 02/17] tests: Use '+=' to add additional tests, not '=', David Gibson, 2016/06/23
- [Qemu-devel] [PULL 01/17] powerpc/mm: Update the WIMG check during H_ENTER, David Gibson, 2016/06/23
- [Qemu-devel] [PULL 06/17] memory: Add reporting of supported page sizes, David Gibson, 2016/06/23
- [Qemu-devel] [PULL 17/17] ppc: Disable huge page support if it is not available for main RAM, David Gibson, 2016/06/23
- [Qemu-devel] [PULL 03/17] ppc64: disable gen_pause() for linux-user mode, David Gibson, 2016/06/23
- [Qemu-devel] [PULL 07/17] ppc: Fix rfi/rfid/hrfi/... emulation, David Gibson, 2016/06/23
- [Qemu-devel] [PULL 09/17] ppc: fix exception model for HV mode, David Gibson, 2016/06/23
- [Qemu-devel] [PULL 05/17] ppc: Improve emulation of THRM registers, David Gibson, 2016/06/23
- [Qemu-devel] [PULL 11/17] ppc: Fix generation if ISI/DSI vs. HV mode, David Gibson, 2016/06/23
- [Qemu-devel] [PULL 14/17] ppc: Turn a bunch of booleans from int to bool, David Gibson, 2016/06/23
- [Qemu-devel] [PULL 08/17] ppc: define a default LPCR value,
David Gibson <=
- [Qemu-devel] [PULL 15/17] ppc: Move exception generation code out of line, David Gibson, 2016/06/23
- [Qemu-devel] [PULL 12/17] ppc: Rework generation of priv and inval interrupts, David Gibson, 2016/06/23
- [Qemu-devel] [PULL 10/17] ppc: Fix POWER7 and POWER8 exception definitions, David Gibson, 2016/06/23
- [Qemu-devel] [PULL 16/17] ppc: Add P7/P8 Power Management instructions, David Gibson, 2016/06/23
- [Qemu-devel] [PULL 13/17] ppc: Add real mode CI load/store instructions for P7 and P8, David Gibson, 2016/06/23
- [Qemu-devel] [PULL 04/17] target-ppc: Fix rlwimi, rlwinm, rlwnm again, David Gibson, 2016/06/23
- Re: [Qemu-devel] [PULL 00/17] ppc-for-2.7 queue 20160623, Peter Maydell, 2016/06/23