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[Qemu-devel] [PULL 04/10] softfloat: Handle snan_bit_is_one == 0 in MIPS
From: |
Leon Alrae |
Subject: |
[Qemu-devel] [PULL 04/10] softfloat: Handle snan_bit_is_one == 0 in MIPS pickNaNMulAdd() |
Date: |
Sun, 26 Jun 2016 14:38:36 +0100 |
From: Aleksandar Markovic <address@hidden>
Only for Mips platform, and only for cases when snan_bit_is_one is 0,
correct the order of argument comparisons in pickNaNMulAdd().
For more info, see [1], page 53, section "3.5.3 NaN Propagation".
[1] "MIPS Architecture for Programmers Volume IV-j:
The MIPS32 SIMD Architecture Module",
Imagination Technologies LTD, Revision 1.12, February 3, 2016
Signed-off-by: Aleksandar Markovic <address@hidden>
Reviewed-by: Leon Alrae <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
address@hidden:
* reworded the subject of the patch
* swapped if/else code blocks to match the commit description]
Signed-off-by: Leon Alrae <address@hidden>
---
fpu/softfloat-specialize.h | 41 +++++++++++++++++++++++++++++------------
1 file changed, 29 insertions(+), 12 deletions(-)
diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
index a1bcb46..43d0890 100644
--- a/fpu/softfloat-specialize.h
+++ b/fpu/softfloat-specialize.h
@@ -571,19 +571,36 @@ static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag
bIsQNaN, flag bIsSNaN,
return 3;
}
- /* Prefer sNaN over qNaN, in the a, b, c order. */
- if (aIsSNaN) {
- return 0;
- } else if (bIsSNaN) {
- return 1;
- } else if (cIsSNaN) {
- return 2;
- } else if (aIsQNaN) {
- return 0;
- } else if (bIsQNaN) {
- return 1;
+ if (status->snan_bit_is_one) {
+ /* Prefer sNaN over qNaN, in the a, b, c order. */
+ if (aIsSNaN) {
+ return 0;
+ } else if (bIsSNaN) {
+ return 1;
+ } else if (cIsSNaN) {
+ return 2;
+ } else if (aIsQNaN) {
+ return 0;
+ } else if (bIsQNaN) {
+ return 1;
+ } else {
+ return 2;
+ }
} else {
- return 2;
+ /* Prefer sNaN over qNaN, in the c, a, b order. */
+ if (cIsSNaN) {
+ return 2;
+ } else if (aIsSNaN) {
+ return 0;
+ } else if (bIsSNaN) {
+ return 1;
+ } else if (cIsQNaN) {
+ return 2;
+ } else if (aIsQNaN) {
+ return 0;
+ } else {
+ return 1;
+ }
}
}
#elif defined(TARGET_PPC)
--
2.7.4
- [Qemu-devel] [PULL 00/10] target-mips queue, Leon Alrae, 2016/06/26
- [Qemu-devel] [PULL 02/10] softfloat: Clean code format in fpu/softfloat-specialize.h, Leon Alrae, 2016/06/26
- [Qemu-devel] [PULL 03/10] softfloat: For Mips only, correct default NaN values, Leon Alrae, 2016/06/26
- [Qemu-devel] [PULL 04/10] softfloat: Handle snan_bit_is_one == 0 in MIPS pickNaNMulAdd(),
Leon Alrae <=
- [Qemu-devel] [PULL 05/10] linux-user: Update preprocessor constants for Mips-specific e_flags bits, Leon Alrae, 2016/06/26
- [Qemu-devel] [PULL 06/10] target-mips: Activate IEEE 754-2008 signaling NaN bit meaning for MSA, Leon Alrae, 2016/06/26
- [Qemu-devel] [PULL 07/10] target-mips: Add abs2008 flavor of <ABS|NEG>.<S|D>, Leon Alrae, 2016/06/26
- [Qemu-devel] [PULL 01/10] softfloat: Implement run-time-configurable meaning of signaling NaN bit, Leon Alrae, 2016/06/26
- [Qemu-devel] [PULL 08/10] target-mips: Add nan2008 flavor of <CEIL|CVT|FLOOR|ROUND|TRUNC>.<L|W>.<S|D>, Leon Alrae, 2016/06/26
- [Qemu-devel] [PULL 09/10] target-mips: Implement FCR31's R/W bitmask and related functionalities, Leon Alrae, 2016/06/26
- [Qemu-devel] [PULL 10/10] target-mips: Add FCR31's FS bit definition, Leon Alrae, 2016/06/26
- Re: [Qemu-devel] [PULL 00/10] target-mips queue, Peter Maydell, 2016/06/27