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[Qemu-devel] [PULL 04/18] cadence_gem: Set the last bit when wrap is set
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 04/18] cadence_gem: Set the last bit when wrap is set |
Date: |
Mon, 27 Jun 2016 15:44:56 +0100 |
From: Alistair Francis <address@hidden>
The Cadence GEM data sheet says:
"Wrap - marks last descriptor in transmit buffer descriptor list. This
can be set for any buffer within the frame."
which seems to imply that when the wrap bit is set so is the last bit.
Previously if the wrap bit is set, but the last is not then QEMU will
enter an infinite loop.
Signed-off-by: Alistair Francis <address@hidden>
Reported-by: Li Qiang <address@hidden>
Reported-by: P J P <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
hw/net/cadence_gem.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index e5f3c98..8a4be1e 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -274,6 +274,11 @@ static inline unsigned tx_desc_get_last(unsigned *desc)
return (desc[1] & DESC_1_TX_LAST) ? 1 : 0;
}
+static inline void tx_desc_set_last(unsigned *desc)
+{
+ desc[1] |= DESC_1_TX_LAST;
+}
+
static inline unsigned tx_desc_get_length(unsigned *desc)
{
return desc[1] & DESC_1_LENGTH;
@@ -939,6 +944,7 @@ static void gem_transmit(CadenceGEMState *s)
/* read next descriptor */
if (tx_desc_get_wrap(desc)) {
+ tx_desc_set_last(desc);
packet_desc_addr = s->regs[GEM_TXQBASE];
} else {
packet_desc_addr += 8;
--
1.9.1
- [Qemu-devel] [PULL 14/18] m25p80: Introduce quad and equad modes., (continued)
- [Qemu-devel] [PULL 14/18] m25p80: Introduce quad and equad modes., Peter Maydell, 2016/06/27
- [Qemu-devel] [PULL 09/18] m25p80: Replace JEDEC ID masking with function., Peter Maydell, 2016/06/27
- [Qemu-devel] [PULL 07/18] ast2400: Integrate the SCU model and set silicon revision, Peter Maydell, 2016/06/27
- [Qemu-devel] [PULL 15/18] m25p80: Introduce configuration registers., Peter Maydell, 2016/06/27
- [Qemu-devel] [PULL 08/18] palmetto-bmc: Configure the SCU's hardware strapping register, Peter Maydell, 2016/06/27
- [Qemu-devel] [PULL 05/18] arm: Re-enable tmp105 test, Peter Maydell, 2016/06/27
- [Qemu-devel] [PULL 18/18] m25p80: Fix WINBOND fast read command handling, Peter Maydell, 2016/06/27
- [Qemu-devel] [PULL 10/18] m25p80: Make a table for JEDEC ID., Peter Maydell, 2016/06/27
- [Qemu-devel] [PULL 13/18] m25p80: Add additional flash commands:, Peter Maydell, 2016/06/27
- [Qemu-devel] [PULL 12/18] m25p80: Introduce COLLECTING_VAR_LEN_DATA state., Peter Maydell, 2016/06/27
- [Qemu-devel] [PULL 04/18] cadence_gem: Set the last bit when wrap is set,
Peter Maydell <=
- [Qemu-devel] [PULL 01/18] hw/intc/arm_gicv3: Add missing break, Peter Maydell, 2016/06/27
- [Qemu-devel] [PULL 11/18] m25p80: Allow more than four banks., Peter Maydell, 2016/06/27
- [Qemu-devel] [PULL 02/18] cadence_uart: Protect against transmit errors, Peter Maydell, 2016/06/27
- [Qemu-devel] [PULL 17/18] m25p80: New flash devices., Peter Maydell, 2016/06/27
- [Qemu-devel] [PULL 06/18] hw/misc: Add a model for the ASPEED System Control Unit, Peter Maydell, 2016/06/27
- [Qemu-devel] [PULL 03/18] cadence_gem: Avoid infinite loops with a misconfigured buffer, Peter Maydell, 2016/06/27
- Re: [Qemu-devel] [PULL 00/18] target-arm queue, Peter Maydell, 2016/06/27