[Qemu-devel] [PATCH 0/4] target-mips: add extended ASID support

[Leon Alrae]

Currently we assume 8-bit ASID everywhere in target-mips code, whereas
MIPS architecture allows greater ASIDs. If CP0.Config4.AE bit is set then
EntryHi.ASID is extended to 10 bits. This feature is present in real I6400
CPU therefore implement and enable it in emulated by QEMU I6400 model.

This series is based on the patch adding I6400 CPU:
https://lists.gnu.org/archive/html/qemu-devel/2016-06/msg07604.html

Thanks,
Leon

Leon Alrae (1):
  target-mips: enable 10-bit ASIDs in I6400 CPU

Paul Burton (3):
  target-mips: add ASID mask field and replace magic values
  target-mips: change ASID type to hold more than 8 bits
  target-mips: support CP0.Config4.AE bit

 target-mips/cpu.h            |  5 ++++-
 target-mips/helper.c         | 10 +++++-----
 target-mips/machine.c        | 10 +++++-----
 target-mips/op_helper.c      | 33 ++++++++++++++++++---------------
 target-mips/translate.c      |  2 ++
 target-mips/translate_init.c |  2 +-
 6 files changed, 35 insertions(+), 27 deletions(-)

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2.7.4