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[Qemu-devel] [RFC 01/30] softmmu: add cmpxchg helpers
From: |
Emilio G. Cota |
Subject: |
[Qemu-devel] [RFC 01/30] softmmu: add cmpxchg helpers |
Date: |
Mon, 27 Jun 2016 15:01:47 -0400 |
Signed-off-by: Emilio G. Cota <address@hidden>
---
softmmu_template.h | 58 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
tcg/tcg.h | 16 +++++++++++++++
2 files changed, 74 insertions(+)
diff --git a/softmmu_template.h b/softmmu_template.h
index 208f808..7b519dc 100644
--- a/softmmu_template.h
+++ b/softmmu_template.h
@@ -548,6 +548,64 @@ void probe_write(CPUArchState *env, target_ulong addr, int
mmu_idx,
}
}
#endif
+
+DATA_TYPE
+glue(glue(helper_cmpxchg, SUFFIX),
+ MMUSUFFIX)(CPUArchState *env, target_ulong addr, DATA_TYPE old,
+ DATA_TYPE new, TCGMemOpIdx oi, uintptr_t retaddr)
+{
+ unsigned mmu_idx = get_mmuidx(oi);
+ int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
+ target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
+ uintptr_t haddr;
+
+ /* Adjust the given return address. */
+ retaddr -= GETPC_ADJ;
+
+ /* If the TLB entry is for a different page, reload and try again. */
+ if ((addr & TARGET_PAGE_MASK)
+ != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
+ if (unlikely((addr & (DATA_SIZE - 1)) != 0
+ && (get_memop(oi) & MO_AMASK) == MO_ALIGN)) {
+ cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
+ mmu_idx, retaddr);
+ }
+ if (!VICTIM_TLB_HIT(addr_write)) {
+ tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr);
+ }
+ tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
+ }
+
+ /* Handle an IO access. */
+ if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
+ /* XXX */
+ abort();
+ }
+
+ /* Handle slow unaligned access (it spans two pages or IO). */
+ if (DATA_SIZE > 1
+ && unlikely((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1
+ >= TARGET_PAGE_SIZE)) {
+ if ((get_memop(oi) & MO_AMASK) == MO_ALIGN) {
+ cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
+ mmu_idx, retaddr);
+ }
+ }
+
+ /* Handle aligned access or unaligned access in the same page. */
+ if (unlikely((addr & (DATA_SIZE - 1)) != 0
+ && (get_memop(oi) & MO_AMASK) == MO_ALIGN)) {
+ cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
+ mmu_idx, retaddr);
+ }
+ /*
+ * If the host allows unaligned accesses, then let the compiler
+ * do its thing when performing the access on the host.
+ */
+ haddr = addr + env->tlb_table[mmu_idx][index].addend;
+ return atomic_cmpxchg((DATA_TYPE *)haddr, old, new);
+}
+
#endif /* !defined(SOFTMMU_CODE_ACCESS) */
#undef READ_ACCESS_TYPE
diff --git a/tcg/tcg.h b/tcg/tcg.h
index 66d7fc0..1fd7ec3 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -1101,6 +1101,22 @@ uint64_t helper_be_ldq_cmmu(CPUArchState *env,
target_ulong addr,
# define helper_ret_ldq_cmmu helper_le_ldq_cmmu
#endif
+uint8_t helper_cmpxchgb_mmu(CPUArchState *env, target_ulong addr,
+ uint8_t old, uint8_t new,
+ TCGMemOpIdx oi, uintptr_t retaddr);
+
+uint16_t helper_cmpxchgw_mmu(CPUArchState *env, target_ulong addr,
+ uint16_t old, uint16_t new,
+ TCGMemOpIdx oi, uintptr_t retaddr);
+
+uint32_t helper_cmpxchgl_mmu(CPUArchState *env, target_ulong addr,
+ uint32_t old, uint32_t new,
+ TCGMemOpIdx oi, uintptr_t retaddr);
+
+uint64_t helper_cmpxchgq_mmu(CPUArchState *env, target_ulong addr,
+ uint64_t old, uint64_t new,
+ TCGMemOpIdx oi, uintptr_t retaddr);
+
#endif /* CONFIG_SOFTMMU */
#endif /* TCG_H */
--
2.5.0
[Qemu-devel] [RFC 03/30] cpu_ldst: add cpu_cmpxchg helpers, Emilio G. Cota, 2016/06/27
[Qemu-devel] [RFC 02/30] tcg: add tcg_cmpxchg_lock, Emilio G. Cota, 2016/06/27