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[Qemu-devel] [PULL 05/32] Q35: implement property interfece to several p
From: |
Paolo Bonzini |
Subject: |
[Qemu-devel] [PULL 05/32] Q35: implement property interfece to several parameters |
Date: |
Tue, 28 Jun 2016 19:33:35 +0200 |
From: Efimov Vasily <address@hidden>
During creation of Q35 instance several parameters are set using direct access.
It violates Qemu device model. Correctly, the parameters should be handled as
object properties.
The patch adds four link type properties for fields:
mch.ram_memory
mch.pci_address_space
mch.system_memory
mch.address_space_io
And, it adds two size type properties for fields:
mch.below_4g_mem_size
mch.above_4g_mem_size
Signed-off-by: Efimov Vasily <address@hidden>
Signed-off-by: Paolo Bonzini <address@hidden>
---
hw/pci-host/q35.c | 20 ++++++++++++++++++++
include/hw/i386/pc.h | 2 ++
include/hw/pci-host/q35.h | 9 +++++++--
3 files changed, 29 insertions(+), 2 deletions(-)
diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c
index 70f897e..03be05d 100644
--- a/hw/pci-host/q35.c
+++ b/hw/pci-host/q35.c
@@ -127,6 +127,10 @@ static Property mch_props[] = {
DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, Q35PCIHost,
mch.pci_hole64_size, DEFAULT_PCI_HOLE64_SIZE),
DEFINE_PROP_UINT32("short_root_bus", Q35PCIHost, mch.short_root_bus, 0),
+ DEFINE_PROP_SIZE(PCI_HOST_BELOW_4G_MEM_SIZE, Q35PCIHost,
+ mch.below_4g_mem_size, 0),
+ DEFINE_PROP_SIZE(PCI_HOST_ABOVE_4G_MEM_SIZE, Q35PCIHost,
+ mch.above_4g_mem_size, 0),
DEFINE_PROP_END_OF_LIST(),
};
@@ -177,6 +181,22 @@ static void q35_host_initfn(Object *obj)
q35_host_get_mmcfg_size,
NULL, NULL, NULL, NULL);
+ object_property_add_link(obj, MCH_HOST_PROP_RAM_MEM, TYPE_MEMORY_REGION,
+ (Object **) &s->mch.ram_memory,
+ qdev_prop_allow_set_link_before_realize, 0, NULL);
+
+ object_property_add_link(obj, MCH_HOST_PROP_PCI_MEM, TYPE_MEMORY_REGION,
+ (Object **) &s->mch.pci_address_space,
+ qdev_prop_allow_set_link_before_realize, 0, NULL);
+
+ object_property_add_link(obj, MCH_HOST_PROP_SYSTEM_MEM, TYPE_MEMORY_REGION,
+ (Object **) &s->mch.system_memory,
+ qdev_prop_allow_set_link_before_realize, 0, NULL);
+
+ object_property_add_link(obj, MCH_HOST_PROP_IO_MEM, TYPE_MEMORY_REGION,
+ (Object **) &s->mch.address_space_io,
+ qdev_prop_allow_set_link_before_realize, 0, NULL);
+
/* Leave enough space for the biggest MCFG BAR */
/* TODO: this matches current bios behaviour, but
* it's not a power of two, which means an MTRR
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index bc85054..f806be4 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -240,6 +240,8 @@ void pc_guest_info_init(PCMachineState *pcms);
#define PCI_HOST_PROP_PCI_HOLE64_START "pci-hole64-start"
#define PCI_HOST_PROP_PCI_HOLE64_END "pci-hole64-end"
#define PCI_HOST_PROP_PCI_HOLE64_SIZE "pci-hole64-size"
+#define PCI_HOST_BELOW_4G_MEM_SIZE "below-4g-mem-size"
+#define PCI_HOST_ABOVE_4G_MEM_SIZE "above-4g-mem-size"
#define DEFAULT_PCI_HOLE64_SIZE (~0x0ULL)
diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h
index c5c073d..1075f3e 100644
--- a/include/hw/pci-host/q35.h
+++ b/include/hw/pci-host/q35.h
@@ -56,8 +56,8 @@ typedef struct MCHPCIState {
MemoryRegion smram, low_smram, high_smram;
MemoryRegion tseg_blackhole, tseg_window;
PcPciInfo pci_info;
- ram_addr_t below_4g_mem_size;
- ram_addr_t above_4g_mem_size;
+ uint64_t below_4g_mem_size;
+ uint64_t above_4g_mem_size;
uint64_t pci_hole64_size;
uint32_t short_root_bus;
IntelIOMMUState *iommu;
@@ -78,6 +78,11 @@ typedef struct Q35PCIHost {
* gmch part
*/
+#define MCH_HOST_PROP_RAM_MEM "ram-mem"
+#define MCH_HOST_PROP_PCI_MEM "pci-mem"
+#define MCH_HOST_PROP_SYSTEM_MEM "system-mem"
+#define MCH_HOST_PROP_IO_MEM "io-mem"
+
/* PCI configuration */
#define MCH_HOST_BRIDGE "MCH"
--
2.7.4
- [Qemu-devel] [PULL 00/32] Misc patches for QEMU soft freeze, Paolo Bonzini, 2016/06/28
- [Qemu-devel] [PULL 01/32] ide: move headers to include folder, Paolo Bonzini, 2016/06/28
- [Qemu-devel] [PULL 02/32] pcspk: convert "pit" property type from ptr to link, Paolo Bonzini, 2016/06/28
- [Qemu-devel] [PULL 03/32] vmport: identify vmport type by macro TYPE_VMPORT, Paolo Bonzini, 2016/06/28
- [Qemu-devel] [PULL 05/32] Q35: implement property interfece to several parameters,
Paolo Bonzini <=
- [Qemu-devel] [PULL 06/32] pc_q35: configure Q35 instance using properties, Paolo Bonzini, 2016/06/28
- [Qemu-devel] [PULL 04/32] pflash: make TYPE_CFI_PFLASH0{1, 2} macros public, Paolo Bonzini, 2016/06/28
- [Qemu-devel] [PULL 07/32] pckbd: handle A20 IRQ as GPIO, Paolo Bonzini, 2016/06/28
- [Qemu-devel] [PULL 08/32] port92: handle A20 IRQ as GPIO, Paolo Bonzini, 2016/06/28
- [Qemu-devel] [PULL 09/32] ICH9 SMB: make TYPE_ICH9_SMB_DEVICE macro public, Paolo Bonzini, 2016/06/28
- [Qemu-devel] [PULL 11/32] ich9: clean up ich9_lpc_update_pic/ich9_lpc_update_apic and callers, Paolo Bonzini, 2016/06/28
- [Qemu-devel] [PULL 12/32] ich9: unify pic and ioapic IRQ vectors, Paolo Bonzini, 2016/06/28
- [Qemu-devel] [PULL 10/32] ich9: call ich9_lpc_update_pic for disabled pirqs, Paolo Bonzini, 2016/06/28
- [Qemu-devel] [PULL 13/32] ICH9 LPC: handle GSI as qdev GPIO, Paolo Bonzini, 2016/06/28
- [Qemu-devel] [PULL 14/32] ICH9 LPC: move call of isa_bus_irqs to 'realize' method, Paolo Bonzini, 2016/06/28