Re: [Qemu-devel] [PATCH] target-i386: Use struct X86XSaveArea in fpu_helper.c

[Eduardo Habkost]

On Sat, Jul 02, 2016 at 04:45:11PM -0700, Richard Henderson wrote:
> On 07/02/2016 01:02 PM, Eduardo Habkost wrote:
> > On Sat, Jul 02, 2016 at 09:44:31AM -0700, Richard Henderson wrote:
> > [...]
> > > @@ -1402,9 +1409,8 @@ void helper_xrstor(CPUX86State *env, target_ulong 
> > > ptr, uint64_t rfbm)
> > >      }
> > > 
> > >      /* The XCOMP field must be zero.  */
> > > -    xcomp_bv0 = cpu_ldq_data_ra(env, ptr + 520, ra);
> > > -    xcomp_bv1 = cpu_ldq_data_ra(env, ptr + 528, ra);
> > > -    if (xcomp_bv0 || xcomp_bv1) {
> > > +    xcomp_bv = cpu_ldq_data_ra(env, ptr + XO(header.xcomp_bv), ra);
> > > +    if (xcomp_bv) {
> > >          raise_exception_ra(env, EXCP0D_GPF, ra);
> > 
> > You are changing the code to not check bytes 528-535 (bytes 16:23
> > of the XSAVE header) anymore, but Intel SDM says XRSTOR raises
> > #GP "If the standard form is executed and bytes 23:8 of the XSAVE
> > header are not all zero."
> 
> Hmm.  I must have an out-of-date version here, since mine just mentions the
> first 8 bytes, and I thought the current definition of X86XSaveHeader backed
> that up.
> 
> I can certainly modify the structure...

I was looking at a September 2015 version (Order Number
325462-056US). It is a bit confusing, because the header layout
documentation (Section 13.4.2) just says bytes 63:16 are
reserved, but the Instruction Set Reference for XRSTOR has the
following:

  Protected Mode Exceptions
  #GP(0)  [...]
          If the standard form is executed and bytes 23:8 of the
          XSAVE header are not all zero.

-- 
Eduardo