Re: [Qemu-devel] [PATCH v9 00/10] 8bit AVR cores

[Michael Rolnik]

actually registers in the range [0x0020 - 0x0060) have dual access through
ST/LD and OUT/IN
registers in the range [0x0000 - 0x0020) have dual access through ST/LD and
CPU
registers in the range [0x0060 - 0x0100) can be accessed by LD/ST only.

we can create memory device, however it will cover the whole range [0x0000
- 0x0100), or we can create io device.

On Wed, Jul 6, 2016 at 12:54 PM, Peter Maydell <address@hidden>
wrote:

> On 6 July 2016 at 10:49, Michael Rolnik <address@hidden> wrote:
> > in the range [0x0000 - 0x0100)
> > some registers are owned by the CPU and some by board devices.
> > CPU registers will be accessed by helper_fullrd & helper_fullwr whereas
> > device registers e.g. USB, will be handled by USB provided it's possible
> to
> > add rd/wr handlers for specific io addresses.
>
> Something like USB which is conceptually separate from the
> CPU itself can be implemented as its own device which is mapped
> in to the right place in the memory map. You probably want an
> "SoC" container device which maps all the various devices
> into the right place, and then every board which uses that
> particular chip doesn't need to duplicate that code.
> There are plenty of examples of this kind of thing: try
> the ARM imx boards or the xilinx ones.
>
> thanks
> -- PMM
>



-- 
Best Regards,
Michael Rolnik