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Re: [Qemu-devel] [PATCH v10 01/10] target-avr: AVR cores support is adde
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH v10 01/10] target-avr: AVR cores support is added. |
Date: |
Wed, 13 Jul 2016 08:27:10 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.1.1 |
On 07/13/2016 05:35 AM, Michael Rolnik wrote:
> a. a helper function sets a flag within env
... and exits the cpu loop.
> b. cpu_get_tb_cpu_state introduces this flag, though tb.flags, for code
> generation by gen_intermediate_code
> c. the code is generated
Yep.
> d. the flag remains to be set within env. Who clear it?
Presumably this flag is only usefully set for one instruction, the one we've
just determined accesses the registers. So I'd clear the flag within
helper_fullwr / helper_fullrd.
In translate.c, when you notice tb->flags & HF_FULLACC is set, you'd interpret
one instruction and then exit the TB. That way we'll start the next TB with
HF_FULLACC cleared.
Thus for a series of instructions like
insn1
insn2
insn3 (writes to register)
insn4
branch
we will generate 3 TB:
TB1: (flags = 0)
insn1
insn2
insn3
insn4
branch
TB2: (flags = HF_FULLACC)
insn3
TB3: (flags = 0)
insn4
branch
Most importantly, when we come to execute TB1 for the second time, we will find
TB2 and TB3 quickly, with the right set of flags.
r~
[Qemu-devel] [PATCH v10 05/10] target-avr: adding AVR interrupt handling, Michael Rolnik, 2016/07/06
[Qemu-devel] [PATCH v10 06/10] target-avr: adding helpers for IN, OUT, SLEEP, WBR & unsupported instructions, Michael Rolnik, 2016/07/06
[Qemu-devel] [PATCH v10 04/10] target-avr: adding instructions encodings, Michael Rolnik, 2016/07/06
[Qemu-devel] [PATCH v10 07/10] target-avr: adding instruction decoder, Michael Rolnik, 2016/07/06
[Qemu-devel] [PATCH v10 09/10] target-avr: updating translate.c to use instructions translation, Michael Rolnik, 2016/07/06