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[Qemu-devel] [PULL v2 18/55] intel_iommu: handle interrupt remap enable
From: |
Michael S. Tsirkin |
Subject: |
[Qemu-devel] [PULL v2 18/55] intel_iommu: handle interrupt remap enable |
Date: |
Tue, 19 Jul 2016 20:52:05 +0300 |
From: Peter Xu <address@hidden>
Handle writting to IRE bit in global command register.
Signed-off-by: Peter Xu <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Signed-off-by: Michael S. Tsirkin <address@hidden>
---
hw/i386/intel_iommu.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index bf74533..6a6cb3b 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -1183,6 +1183,22 @@ static void vtd_handle_gcmd_te(IntelIOMMUState *s, bool
en)
}
}
+/* Handle Interrupt Remap Enable/Disable */
+static void vtd_handle_gcmd_ire(IntelIOMMUState *s, bool en)
+{
+ VTD_DPRINTF(CSR, "Interrupt Remap Enable %s", (en ? "on" : "off"));
+
+ if (en) {
+ s->intr_enabled = true;
+ /* Ok - report back to driver */
+ vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_IRES);
+ } else {
+ s->intr_enabled = false;
+ /* Ok - report back to driver */
+ vtd_set_clear_mask_long(s, DMAR_GSTS_REG, VTD_GSTS_IRES, 0);
+ }
+}
+
/* Handle write to Global Command Register */
static void vtd_handle_gcmd_write(IntelIOMMUState *s)
{
@@ -1207,6 +1223,10 @@ static void vtd_handle_gcmd_write(IntelIOMMUState *s)
/* Set/update the interrupt remapping root-table pointer */
vtd_handle_gcmd_sirtp(s);
}
+ if (changed & VTD_GCMD_IRE) {
+ /* Interrupt remap enable/disable */
+ vtd_handle_gcmd_ire(s, val & VTD_GCMD_IRE);
+ }
}
/* Handle write to Context Command Register */
--
MST
- [Qemu-devel] [PULL v2 08/55] hw/versatile: realize the PCI root bus as part of the versatile init, (continued)
- [Qemu-devel] [PULL v2 08/55] hw/versatile: realize the PCI root bus as part of the versatile init, Michael S. Tsirkin, 2016/07/19
- [Qemu-devel] [PULL v2 09/55] x86-iommu: introduce parent class, Michael S. Tsirkin, 2016/07/19
- [Qemu-devel] [PULL v2 10/55] intel_iommu: rename VTD_PCI_DEVFN_MAX to x86-iommu, Michael S. Tsirkin, 2016/07/19
- [Qemu-devel] [PULL v2 11/55] x86-iommu: provide x86_iommu_get_default, Michael S. Tsirkin, 2016/07/19
- [Qemu-devel] [PULL v2 12/55] x86-iommu: introduce "intremap" property, Michael S. Tsirkin, 2016/07/19
- [Qemu-devel] [PULL v2 13/55] acpi: enable INTR for DMAR report structure, Michael S. Tsirkin, 2016/07/19
- [Qemu-devel] [PULL v2 14/55] intel_iommu: allow queued invalidation for IR, Michael S. Tsirkin, 2016/07/19
- [Qemu-devel] [PULL v2 15/55] intel_iommu: set IR bit for ECAP register, Michael S. Tsirkin, 2016/07/19
- [Qemu-devel] [PULL v2 16/55] acpi: add DMAR scope definition for root IOAPIC, Michael S. Tsirkin, 2016/07/19
- [Qemu-devel] [PULL v2 17/55] intel_iommu: define interrupt remap table addr register, Michael S. Tsirkin, 2016/07/19
- [Qemu-devel] [PULL v2 18/55] intel_iommu: handle interrupt remap enable,
Michael S. Tsirkin <=
- [Qemu-devel] [PULL v2 19/55] intel_iommu: define several structs for IOMMU IR, Michael S. Tsirkin, 2016/07/19
- [Qemu-devel] [PULL v2 20/55] intel_iommu: add IR translation faults defines, Michael S. Tsirkin, 2016/07/19
- [Qemu-devel] [PULL v2 21/55] intel_iommu: Add support for PCI MSI remap, Michael S. Tsirkin, 2016/07/19
- [Qemu-devel] [PULL v2 22/55] q35: ioapic: add support for emulated IOAPIC IR, Michael S. Tsirkin, 2016/07/19
- [Qemu-devel] [PULL v2 23/55] ioapic: introduce ioapic_entry_parse() helper, Michael S. Tsirkin, 2016/07/19
- [Qemu-devel] [PULL v2 24/55] intel_iommu: add support for split irqchip, Michael S. Tsirkin, 2016/07/19
- [Qemu-devel] [PULL v2 25/55] x86-iommu: introduce IEC notifiers, Michael S. Tsirkin, 2016/07/19
- [Qemu-devel] [PULL v2 26/55] ioapic: register IOMMU IEC notifier for ioapic, Michael S. Tsirkin, 2016/07/19
- [Qemu-devel] [PULL v2 27/55] intel_iommu: Add support for Extended Interrupt Mode, Michael S. Tsirkin, 2016/07/19
- [Qemu-devel] [PULL v2 28/55] intel_iommu: add SID validation for IR, Michael S. Tsirkin, 2016/07/19