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[Qemu-devel] [PULL v5 22/57] intel_iommu: get rid of {0} initializers
From: |
Michael S. Tsirkin |
Subject: |
[Qemu-devel] [PULL v5 22/57] intel_iommu: get rid of {0} initializers |
Date: |
Thu, 21 Jul 2016 20:52:45 +0300 |
Correct and portable in theory, but triggers warnings with older gcc
versions when -Wmissing-braces is enabled.
See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=53119
Signed-off-by: Michael S. Tsirkin <address@hidden>
---
hw/i386/intel_iommu.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 2e57396..ccfcc69 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -2024,7 +2024,7 @@ static int vtd_irte_get(IntelIOMMUState *iommu, uint16_t
index,
/* Fetch IRQ information of specific IR index */
static int vtd_remap_irq_get(IntelIOMMUState *iommu, uint16_t index, VTDIrq
*irq)
{
- VTD_IRTE irte = { 0 };
+ VTD_IRTE irte = {};
int ret = 0;
ret = vtd_irte_get(iommu, index, &irte);
@@ -2082,7 +2082,7 @@ static int vtd_interrupt_remap_msi(IntelIOMMUState *iommu,
int ret = 0;
VTD_IR_MSIAddress addr;
uint16_t index;
- VTDIrq irq = {0};
+ VTDIrq irq = {};
assert(origin && translated);
@@ -2176,7 +2176,7 @@ static MemTxResult vtd_mem_ir_write(void *opaque, hwaddr
addr,
MemTxAttrs attrs)
{
int ret = 0;
- MSIMessage from = {0}, to = {0};
+ MSIMessage from = {}, to = {};
from.address = (uint64_t) addr + VTD_INTERRUPT_ADDR_FIRST;
from.data = (uint32_t) value;
--
MST
- [Qemu-devel] [PULL v5 12/57] x86-iommu: introduce "intremap" property, (continued)
- [Qemu-devel] [PULL v5 12/57] x86-iommu: introduce "intremap" property, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 13/57] acpi: enable INTR for DMAR report structure, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 14/57] intel_iommu: allow queued invalidation for IR, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 15/57] intel_iommu: set IR bit for ECAP register, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 16/57] acpi: add DMAR scope definition for root IOAPIC, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 17/57] intel_iommu: define interrupt remap table addr register, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 18/57] intel_iommu: handle interrupt remap enable, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 19/57] intel_iommu: define several structs for IOMMU IR, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 20/57] intel_iommu: add IR translation faults defines, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 21/57] intel_iommu: Add support for PCI MSI remap, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 22/57] intel_iommu: get rid of {0} initializers,
Michael S. Tsirkin <=
- [Qemu-devel] [PULL v5 23/57] q35: ioapic: add support for emulated IOAPIC IR, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 24/57] ioapic: introduce ioapic_entry_parse() helper, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 25/57] intel_iommu: add support for split irqchip, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 26/57] x86-iommu: introduce IEC notifiers, Michael S. Tsirkin, 2016/07/21
[Qemu-devel] [PULL v5 27/57] ioapic: register IOMMU IEC notifier for ioapic, Michael S. Tsirkin, 2016/07/21
[Qemu-devel] [PULL v5 28/57] intel_iommu: Add support for Extended Interrupt Mode, Michael S. Tsirkin, 2016/07/21