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[Qemu-devel] [PATCH v2 7/8] target-ppc: add vsrv instruction
From: |
Nikunj A Dadhania |
Subject: |
[Qemu-devel] [PATCH v2 7/8] target-ppc: add vsrv instruction |
Date: |
Thu, 28 Jul 2016 23:44:17 +0530 |
From: Vivek Andrew Sha <address@hidden>
Adds Vector Shift Right Variable instruction.
Signed-off-by: Vivek Andrew Sha <address@hidden>
[ reverse the order of computation to avoid temporary array ]
Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 17 +++++++++++++++++
target-ppc/translate/vmx-impl.c | 1 +
target-ppc/translate/vmx-ops.c | 1 +
4 files changed, 20 insertions(+)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index d4c060b..93ac9e1 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -211,6 +211,7 @@ DEF_HELPER_3(vslw, void, avr, avr, avr)
DEF_HELPER_3(vsld, void, avr, avr, avr)
DEF_HELPER_3(vslo, void, avr, avr, avr)
DEF_HELPER_3(vsro, void, avr, avr, avr)
+DEF_HELPER_3(vsrv, void, avr, avr, avr)
DEF_HELPER_3(vslv, void, avr, avr, avr)
DEF_HELPER_3(vaddcuw, void, avr, avr, avr)
DEF_HELPER_3(vsubcuw, void, avr, avr, avr)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index 12fe144..552b2e0 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -1710,6 +1710,23 @@ void helper_vslv(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t
*b)
}
}
+void helper_vsrv(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
+{
+ int i;
+ unsigned int shift, bytes;
+
+ /* Use reverse order, as destination and source register can be same. Its
+ * being modified in place saving temporary, reverse order will guarantee
+ * that computed result is not fed back.
+ */
+ for (i = ARRAY_SIZE(r->u8) - 1; i >= 0; i--) {
+ shift = b->u8[i] & 0x7; /* extract shift value */
+ bytes = ((i ? a->u8[i - 1] : 0) << 8) + a->u8[i];
+ /* extract adjacent bytes */
+ r->u8[i] = (bytes >> shift) & 0xFF; /* shift and store result */
+ }
+}
+
void helper_vsldoi(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t shift)
{
int sh = shift & 0xf;
diff --git a/target-ppc/translate/vmx-impl.c b/target-ppc/translate/vmx-impl.c
index 5844a7e..ac78caf 100644
--- a/target-ppc/translate/vmx-impl.c
+++ b/target-ppc/translate/vmx-impl.c
@@ -367,6 +367,7 @@ GEN_VXFORM(vsrab, 2, 12);
GEN_VXFORM(vsrah, 2, 13);
GEN_VXFORM(vsraw, 2, 14);
GEN_VXFORM(vsrad, 2, 15);
+GEN_VXFORM(vsrv, 2, 28);
GEN_VXFORM(vslv, 2, 29);
GEN_VXFORM(vslo, 6, 16);
GEN_VXFORM(vsro, 6, 17);
diff --git a/target-ppc/translate/vmx-ops.c b/target-ppc/translate/vmx-ops.c
index ffc4443..7449396 100644
--- a/target-ppc/translate/vmx-ops.c
+++ b/target-ppc/translate/vmx-ops.c
@@ -110,6 +110,7 @@ GEN_VXFORM(vsrab, 2, 12),
GEN_VXFORM(vsrah, 2, 13),
GEN_VXFORM(vsraw, 2, 14),
GEN_VXFORM_207(vsrad, 2, 15),
+GEN_VXFORM_300(vsrv, 2, 28),
GEN_VXFORM_300(vslv, 2, 29),
GEN_VXFORM(vslo, 6, 16),
GEN_VXFORM(vsro, 6, 17),
--
2.7.4
- [Qemu-devel] [PATCH v2 0/8] POWER9 TCG enablements - part2, Nikunj A Dadhania, 2016/07/28
- [Qemu-devel] [PATCH v2 1/8] target-ppc: implement branch-less divw[o][.], Nikunj A Dadhania, 2016/07/28
- [Qemu-devel] [PATCH v2 2/8] target-ppc: implement branch-less divd[o][.], Nikunj A Dadhania, 2016/07/28
- [Qemu-devel] [PATCH v2 3/8] target-ppc: add dtstsfi[q] instructions, Nikunj A Dadhania, 2016/07/28
- [Qemu-devel] [PATCH v2 4/8] target-ppc: add vabsdu[b, h, w] instructions, Nikunj A Dadhania, 2016/07/28
- [Qemu-devel] [PATCH v2 5/8] target-ppc: add vcmpnez[b, h, w][.] instructions, Nikunj A Dadhania, 2016/07/28
- [Qemu-devel] [PATCH v2 6/8] target-ppc: add vslv instruction, Nikunj A Dadhania, 2016/07/28
- [Qemu-devel] [PATCH v2 8/8] target-ppc: add extswsli[.] instruction, Nikunj A Dadhania, 2016/07/28
- [Qemu-devel] [PATCH v2 7/8] target-ppc: add vsrv instruction,
Nikunj A Dadhania <=
- Re: [Qemu-devel] [PATCH v2 0/8] POWER9 TCG enablements - part2, David Gibson, 2016/07/29