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Re: [Qemu-devel] [PATCH 28/32] ppc: Avoid double translation for lvx/lvx


From: Richard Henderson
Subject: Re: [Qemu-devel] [PATCH 28/32] ppc: Avoid double translation for lvx/lvxl/stvx/stvxl
Date: Fri, 29 Jul 2016 18:07:55 +0530
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.1.1

On 07/29/2016 12:26 PM, Benjamin Herrenschmidt wrote:
I notice that sadly, all of the vector ops are helper with full
clobbers, because I assume, the "avr" is passed as pointer due to the
lack of an int128 type in TCG correct ?

Yes. Although x86 doesn't declare the vector registers as tcg registers at all. Which is both a blessing and a curse.

My opinion is that aarch64 is the model to aim for -- most operations can operate on 64-bit slices at a time, no registers clobbered. There will always be exceptions, of course, but hopefully with rarer insns.


r~



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