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Re: [Qemu-devel] [PATCH v3 3/5] target-ppc: add vector count trailing ze
From: |
David Gibson |
Subject: |
Re: [Qemu-devel] [PATCH v3 3/5] target-ppc: add vector count trailing zeros instructions |
Date: |
Tue, 16 Aug 2016 14:46:57 +1000 |
User-agent: |
Mutt/1.6.2 (2016-07-01) |
On Thu, Aug 11, 2016 at 01:06:46PM +0530, Rajalakshmi Srinivasaraghavan wrote:
> The following vector count trailing zeros instructions are
> added from ISA 3.0.
>
> vctzb - Vector Count Trailing Zeros Byte
> vctzh - Vector Count Trailing Zeros Halfword
> vctzw - Vector Count Trailing Zeros Word
> vctzd - Vector Count Trailing Zeros Doubleword
>
> Signed-off-by: Rajalakshmi Srinivasaraghavan <address@hidden>
Reviewed-by: David Gibson <address@hidden>
However, it needs a rebase.
> ---
> target-ppc/helper.h | 4 ++++
> target-ppc/int_helper.c | 15 +++++++++++++++
> target-ppc/translate/vmx-impl.c | 19 +++++++++++++++++++
> target-ppc/translate/vmx-ops.c | 8 ++++++++
> 4 files changed, 46 insertions(+), 0 deletions(-)
>
> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> index 59e7b88..6e6e7b3 100644
> --- a/target-ppc/helper.h
> +++ b/target-ppc/helper.h
> @@ -327,6 +327,10 @@ DEF_HELPER_2(vclzb, void, avr, avr)
> DEF_HELPER_2(vclzh, void, avr, avr)
> DEF_HELPER_2(vclzw, void, avr, avr)
> DEF_HELPER_2(vclzd, void, avr, avr)
> +DEF_HELPER_2(vctzb, void, avr, avr)
> +DEF_HELPER_2(vctzh, void, avr, avr)
> +DEF_HELPER_2(vctzw, void, avr, avr)
> +DEF_HELPER_2(vctzd, void, avr, avr)
> DEF_HELPER_2(vpopcntb, void, avr, avr)
> DEF_HELPER_2(vpopcnth, void, avr, avr)
> DEF_HELPER_2(vpopcntw, void, avr, avr)
> diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
> index a917bd5..162f1e9 100644
> --- a/target-ppc/int_helper.c
> +++ b/target-ppc/int_helper.c
> @@ -2091,6 +2091,21 @@ VGENERIC_DO(clzd, u64)
> #undef clzw
> #undef clzd
>
> +#define ctzb(v) ((v) ? ctz32(v) : 8)
> +#define ctzh(v) ((v) ? ctz32(v) : 16)
> +#define ctzw(v) ctz32((v))
> +#define ctzd(v) ctz64((v))
> +
> +VGENERIC_DO(ctzb, u8)
> +VGENERIC_DO(ctzh, u16)
> +VGENERIC_DO(ctzw, u32)
> +VGENERIC_DO(ctzd, u64)
> +
> +#undef ctzb
> +#undef ctzh
> +#undef ctzw
> +#undef ctzd
> +
> #define popcntb(v) ctpop8(v)
> #define popcnth(v) ctpop16(v)
> #define popcntw(v) ctpop32(v)
> diff --git a/target-ppc/translate/vmx-impl.c b/target-ppc/translate/vmx-impl.c
> index 766a645..ebf123f 100644
> --- a/target-ppc/translate/vmx-impl.c
> +++ b/target-ppc/translate/vmx-impl.c
> @@ -553,6 +553,21 @@ static void glue(gen_, name)(DisasContext *ctx)
> \
> tcg_temp_free_ptr(rd); \
> }
>
> +#define GEN_VXFORM_NOA_2(name, opc2, opc3, opc4) \
> +static void glue(gen_, name)(DisasContext *ctx) \
> + { \
> + TCGv_ptr rb, rd; \
> + if (unlikely(!ctx->altivec_enabled)) { \
> + gen_exception(ctx, POWERPC_EXCP_VPU); \
> + return; \
> + } \
> + rb = gen_avr_ptr(rB(ctx->opcode)); \
> + rd = gen_avr_ptr(rD(ctx->opcode)); \
> + gen_helper_##name(rd, rb); \
> + tcg_temp_free_ptr(rb); \
> + tcg_temp_free_ptr(rd); \
> + }
> +
> GEN_VXFORM_NOA(vupkhsb, 7, 8);
> GEN_VXFORM_NOA(vupkhsh, 7, 9);
> GEN_VXFORM_NOA(vupkhsw, 7, 25);
> @@ -745,6 +760,10 @@ GEN_VXFORM_NOA(vclzb, 1, 28)
> GEN_VXFORM_NOA(vclzh, 1, 29)
> GEN_VXFORM_NOA(vclzw, 1, 30)
> GEN_VXFORM_NOA(vclzd, 1, 31)
> +GEN_VXFORM_NOA_2(vctzb, 1, 24, 28)
> +GEN_VXFORM_NOA_2(vctzh, 1, 24, 29)
> +GEN_VXFORM_NOA_2(vctzw, 1, 24, 30)
> +GEN_VXFORM_NOA_2(vctzd, 1, 24, 31)
> GEN_VXFORM_NOA(vpopcntb, 1, 28)
> GEN_VXFORM_NOA(vpopcnth, 1, 29)
> GEN_VXFORM_NOA(vpopcntw, 1, 30)
> diff --git a/target-ppc/translate/vmx-ops.c b/target-ppc/translate/vmx-ops.c
> index aafe70b..5b2826e 100644
> --- a/target-ppc/translate/vmx-ops.c
> +++ b/target-ppc/translate/vmx-ops.c
> @@ -44,6 +44,10 @@ GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000,
> PPC_NONE, PPC2_ISA300)
> #define GEN_VXFORM_300_EXT(name, opc2, opc3, inval) \
> GEN_HANDLER_E(name, 0x04, opc2, opc3, inval, PPC_NONE, PPC2_ISA300)
>
> +#define GEN_VXFORM_300_EO(name, opc2, opc3, opc4) \
> +GEN_HANDLER_E_2(name, 0x04, opc2, opc3, opc4, 0x00000000, PPC_NONE, \
> + PPC2_ISA300)
> +
> #define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \
> GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1)
>
> @@ -211,6 +215,10 @@ GEN_VXFORM_DUAL_INV(vspltish, vinserth, 6, 13,
> 0x00000000, 0x100000,
> GEN_VXFORM_DUAL_INV(vspltisw, vinsertw, 6, 14, 0x00000000, 0x100000,
> PPC2_ALTIVEC_207),
> GEN_VXFORM_300_EXT(vinsertd, 6, 15, 0x100000),
> +GEN_VXFORM_300_EO(vctzb, 0x01, 0x18, 0x1C),
> +GEN_VXFORM_300_EO(vctzh, 0x01, 0x18, 0x1D),
> +GEN_VXFORM_300_EO(vctzw, 0x01, 0x18, 0x1E),
> +GEN_VXFORM_300_EO(vctzd, 0x01, 0x18, 0x1F),
>
> #define GEN_VXFORM_NOA(name, opc2, opc3) \
> GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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- [Qemu-devel] [PATCH v3 3/5] target-ppc: add vector count trailing zeros instructions, Rajalakshmi Srinivasaraghavan, 2016/08/11
- Re: [Qemu-devel] [PATCH v3 3/5] target-ppc: add vector count trailing zeros instructions,
David Gibson <=
- [Qemu-devel] [PATCH v3 4/5] target-ppc: add vector bit permute doubleword instruction, Rajalakshmi Srinivasaraghavan, 2016/08/11
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