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[Qemu-devel] [PULL 51/66] target-ppc: add vslv instruction
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 51/66] target-ppc: add vslv instruction |
Date: |
Tue, 6 Sep 2016 13:43:01 +1000 |
From: Vivek Andrew Sha <address@hidden>
vslv: Vector Shift Left Variable
Signed-off-by: Vivek Andrew Sha <address@hidden>
Signed-off-by: Nikunj A Dadhania <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 14 ++++++++++++++
target-ppc/translate/vmx-impl.c | 1 +
target-ppc/translate/vmx-ops.c | 4 ++++
4 files changed, 20 insertions(+)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index e93b84b..9703f85 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -211,6 +211,7 @@ DEF_HELPER_3(vslw, void, avr, avr, avr)
DEF_HELPER_3(vsld, void, avr, avr, avr)
DEF_HELPER_3(vslo, void, avr, avr, avr)
DEF_HELPER_3(vsro, void, avr, avr, avr)
+DEF_HELPER_3(vslv, void, avr, avr, avr)
DEF_HELPER_3(vaddcuw, void, avr, avr, avr)
DEF_HELPER_3(vsubcuw, void, avr, avr, avr)
DEF_HELPER_2(lvsl, void, avr, tl)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index 9b4de69..12fe144 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -1696,6 +1696,20 @@ VSL(w, u32, 0x1F)
VSL(d, u64, 0x3F)
#undef VSL
+void helper_vslv(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
+{
+ int i;
+ unsigned int shift, bytes, size;
+
+ size = ARRAY_SIZE(r->u8);
+ for (i = 0; i < size; i++) {
+ shift = b->u8[i] & 0x7; /* extract shift value */
+ bytes = (a->u8[i] << 8) + /* extract adjacent bytes */
+ (((i + 1) < size) ? a->u8[i + 1] : 0);
+ r->u8[i] = (bytes << shift) >> 8; /* shift and store result */
+ }
+}
+
void helper_vsldoi(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t shift)
{
int sh = shift & 0xf;
diff --git a/target-ppc/translate/vmx-impl.c b/target-ppc/translate/vmx-impl.c
index 5cd007e..e979668 100644
--- a/target-ppc/translate/vmx-impl.c
+++ b/target-ppc/translate/vmx-impl.c
@@ -383,6 +383,7 @@ GEN_VXFORM(vsrab, 2, 12);
GEN_VXFORM(vsrah, 2, 13);
GEN_VXFORM(vsraw, 2, 14);
GEN_VXFORM(vsrad, 2, 15);
+GEN_VXFORM(vslv, 2, 29);
GEN_VXFORM(vslo, 6, 16);
GEN_VXFORM(vsro, 6, 17);
GEN_VXFORM(vaddcuw, 0, 6);
diff --git a/target-ppc/translate/vmx-ops.c b/target-ppc/translate/vmx-ops.c
index 0be6989..61e08b2 100644
--- a/target-ppc/translate/vmx-ops.c
+++ b/target-ppc/translate/vmx-ops.c
@@ -38,6 +38,9 @@ GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
#define GEN_VXFORM_207(name, opc2, opc3) \
GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
+#define GEN_VXFORM_300(name, opc2, opc3) \
+GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ISA300)
+
#define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \
GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1)
@@ -107,6 +110,7 @@ GEN_VXFORM(vsrab, 2, 12),
GEN_VXFORM(vsrah, 2, 13),
GEN_VXFORM(vsraw, 2, 14),
GEN_VXFORM_207(vsrad, 2, 15),
+GEN_VXFORM_300(vslv, 2, 29),
GEN_VXFORM(vslo, 6, 16),
GEN_VXFORM(vsro, 6, 17),
GEN_VXFORM(vaddcuw, 0, 6),
--
2.7.4
- [Qemu-devel] [PULL 58/66] ppc: Fix catching some segfaults in user mode, (continued)
- [Qemu-devel] [PULL 58/66] ppc: Fix catching some segfaults in user mode, David Gibson, 2016/09/05
- [Qemu-devel] [PULL 20/66] ppc: Move VMX ops out of translate.c, David Gibson, 2016/09/05
- [Qemu-devel] [PULL 17/66] ppc: Move classic fp ops out of translate.c, David Gibson, 2016/09/05
- [Qemu-devel] [PULL 61/66] ppc: Improve flags for helpers loading/writing the time facilities, David Gibson, 2016/09/05
- [Qemu-devel] [PULL 34/66] ppc: Don't update NIP BookE 2.06 tlbwe, David Gibson, 2016/09/05
- [Qemu-devel] [PULL 39/66] ppc: Handle unconditional (always/never) traps at translation time, David Gibson, 2016/09/05
- [Qemu-devel] [PULL 47/66] target-ppc: implement branch-less divd[o][.], David Gibson, 2016/09/05
- [Qemu-devel] [PULL 41/66] ppc: Fix CFAR updates, David Gibson, 2016/09/05
- [Qemu-devel] [PULL 35/66] ppc: Don't update NIP on conditional trap instructions, David Gibson, 2016/09/05
- [Qemu-devel] [PULL 38/66] ppc: Make alignment exceptions suck less, David Gibson, 2016/09/05
- [Qemu-devel] [PULL 51/66] target-ppc: add vslv instruction,
David Gibson <=
- [Qemu-devel] [PULL 65/66] tests: Resort check-qtest entries in Makefile.include, David Gibson, 2016/09/05
- [Qemu-devel] [PULL 55/66] hw/ppc: use error_report instead of fprintf, David Gibson, 2016/09/05
- [Qemu-devel] [PULL 53/66] target-ppc: add extswsli[.] instruction, David Gibson, 2016/09/05
- [Qemu-devel] [PULL 50/66] target-ppc: add vcmpnez[b, h, w][.] instructions, David Gibson, 2016/09/05
- [Qemu-devel] [PULL 48/66] target-ppc: add dtstsfi[q] instructions, David Gibson, 2016/09/05
- [Qemu-devel] [PULL 21/66] ppc: Move VSX ops out of translate.c, David Gibson, 2016/09/05
- [Qemu-devel] [PULL 54/66] ppc: Rename #include'd .c files to .inc.c, David Gibson, 2016/09/05
- [Qemu-devel] [PULL 64/66] spapr: implement H_CHANGE_LOGICAL_LAN_MAC h_call, David Gibson, 2016/09/05
- [Qemu-devel] [PULL 60/66] ppc: Don't generate dead code on unconditional branches, David Gibson, 2016/09/05
- [Qemu-devel] [PULL 66/66] tests: Check serial output of firmware boot of some machines, David Gibson, 2016/09/05