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[Qemu-devel] [PULL 05/18] tcg/i386: Add support for fence
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL 05/18] tcg/i386: Add support for fence |
Date: |
Wed, 7 Sep 2016 14:10:35 -0700 |
From: Pranith Kumar <address@hidden>
Generate a 'lock orl $0,0(%esp)' instruction for ordering instead of
mfence which has similar ordering semantics.
Signed-off-by: Pranith Kumar <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/i386/tcg-target.inc.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
index 1573e69..b4f3223 100644
--- a/tcg/i386/tcg-target.inc.c
+++ b/tcg/i386/tcg-target.inc.c
@@ -686,6 +686,18 @@ static inline void tcg_out_pushi(TCGContext *s,
tcg_target_long val)
}
}
+static inline void tcg_out_mb(TCGContext *s, TCGArg a0)
+{
+ /* Given the strength of x86 memory ordering, we only need care for
+ store-load ordering. Experimentally, "lock orl $0,0(%esp)" is
+ faster than "mfence", so don't bother with the sse insn. */
+ if (a0 & TCG_MO_ST_LD) {
+ tcg_out8(s, 0xf0);
+ tcg_out_modrm_offset(s, OPC_ARITH_EvIb, ARITH_OR, TCG_REG_ESP, 0);
+ tcg_out8(s, 0);
+ }
+}
+
static inline void tcg_out_push(TCGContext *s, int reg)
{
tcg_out_opc(s, OPC_PUSH_r32 + LOWREGMASK(reg), 0, reg, 0);
@@ -2130,6 +2142,9 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode
opc,
}
break;
+ case INDEX_op_mb:
+ tcg_out_mb(s, args[0]);
+ break;
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_mov_i64:
case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
@@ -2195,6 +2210,8 @@ static const TCGTargetOpDef x86_op_defs[] = {
{ INDEX_op_add2_i32, { "r", "r", "0", "1", "ri", "ri" } },
{ INDEX_op_sub2_i32, { "r", "r", "0", "1", "ri", "ri" } },
+ { INDEX_op_mb, { } },
+
#if TCG_TARGET_REG_BITS == 32
{ INDEX_op_brcond2_i32, { "r", "r", "ri", "ri" } },
{ INDEX_op_setcond2_i32, { "r", "r", "r", "ri", "ri" } },
--
2.7.4
- [Qemu-devel] [PULL 00/18] tcg queued patches, Richard Henderson, 2016/09/07
- [Qemu-devel] [PULL 03/18] cpu-exec: Check -dfilter for -d cpu, Richard Henderson, 2016/09/07
- [Qemu-devel] [PULL 02/18] tcg: Merge GETPC and GETRA, Richard Henderson, 2016/09/07
- [Qemu-devel] [PULL 01/18] tcg: Support arbitrary size + alignment, Richard Henderson, 2016/09/07
- [Qemu-devel] [PULL 05/18] tcg/i386: Add support for fence,
Richard Henderson <=
- [Qemu-devel] [PULL 06/18] tcg/aarch64: Add support for fence, Richard Henderson, 2016/09/07
- [Qemu-devel] [PULL 04/18] Introduce TCGOpcode for memory barrier, Richard Henderson, 2016/09/07
- [Qemu-devel] [PULL 07/18] tcg/arm: Add support for fence, Richard Henderson, 2016/09/07
- [Qemu-devel] [PULL 08/18] tcg/ia64: Add support for fence, Richard Henderson, 2016/09/07
- [Qemu-devel] [PULL 09/18] tcg/mips: Add support for fence, Richard Henderson, 2016/09/07
- [Qemu-devel] [PULL 10/18] tcg/ppc: Add support for fence, Richard Henderson, 2016/09/07
- [Qemu-devel] [PULL 11/18] tcg/s390: Add support for fence, Richard Henderson, 2016/09/07
- [Qemu-devel] [PULL 13/18] tcg/tci: Add support for fence, Richard Henderson, 2016/09/07
- [Qemu-devel] [PULL 12/18] tcg/sparc: Add support for fence, Richard Henderson, 2016/09/07
- [Qemu-devel] [PULL 15/18] target-alpha: Generate fence op, Richard Henderson, 2016/09/07