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[Qemu-devel] [PATCH RFC v1 00/29] ARC cores
From: |
Michael Rolnik |
Subject: |
[Qemu-devel] [PATCH RFC v1 00/29] ARC cores |
Date: |
Fri, 9 Sep 2016 01:31:41 +0300 |
This series of patches adds ARC target to QEMU. It indends to support
- ARCtangent-A5 processor
- ARC 600 processor
- ARC 700 processor
All instructions except ASLS are implemented. Not fully tested yet.
However I was able to execute correctly recursive fibonacci calculation.
Reset vector is assumed to be some hardcoded value which worked for my test.
I am planning to get FreeRTOS for ARC, once I get it, I will able to verify
and complete interrupt support.
Michael Rolnik (29):
target-arc: initial commit
target-arc: ADC, ADD, ADD1, ADD2, ADD3
target-arc: SUB, SUB1, SUB2, SUB3, SBC, RSUB, CMP
target-arc: AND, OR, XOR, BIC, TST
target-arc: ASL(m), ASR(m), LSR(m), ROR(m)
target-arc: EX, LD, ST, SYNC, PREFETCH
target-arc: MAX, MIN
target-arc: MOV, EXT, SEX, SWAP
target-arc: NEG, ABS, NOT
target-arc: POP, PUSH
target-arc: BCLR, BMSK, BSET, BTST, BXOR
target-arc: RLC, RRC
target-arc: NORM, NORMW
target-arc: MPY, MPYH, MPYHU, MPYU
target-arc: MUL64, MULU64, DIVAW
target-arc: BBIT0, BBIT1, BR
target-arc: B, BL
target-arc: J, JL
target-arc: LR, SR
target-arc: ADDS, ADDSDW, SUBS, SUBSDW
target-arc: ABSS, ABSSW, NEGS, NEGSW, RND16, SAT16
target-arc: ASLS, ASRS
target-arc: FLAG, BRK, SLEEP
target-arc: NOP, UNIMP
target-arc: TRAP, SWI
target-arc: RTIE
target-arc: LP
target-arc: decode
target-arc: sample board
.gitignore | 2 +
MAINTAINERS | 6 +
arch_init.c | 2 +
configure | 5 +
default-configs/arc-softmmu.mak | 0
hw/arc/Makefile.objs | 21 +
hw/arc/sample.c | 80 ++
include/sysemu/arch_init.h | 1 +
target-arc/Makefile.objs | 28 +
target-arc/cpu-qom.h | 84 ++
target-arc/cpu.c | 269 ++++
target-arc/cpu.h | 174 +++
target-arc/decode.c | 2212 ++++++++++++++++++++++++++++++
target-arc/gdbstub.c | 138 ++
target-arc/helper.c | 74 +
target-arc/helper.h | 29 +
target-arc/machine.c | 35 +
target-arc/machine.h | 21 +
target-arc/op_helper.c | 443 ++++++
target-arc/translate-inst.c | 2855 +++++++++++++++++++++++++++++++++++++++
target-arc/translate-inst.h | 175 +++
target-arc/translate.c | 424 ++++++
target-arc/translate.h | 223 +++
23 files changed, 7301 insertions(+)
create mode 100644 default-configs/arc-softmmu.mak
create mode 100644 hw/arc/Makefile.objs
create mode 100644 hw/arc/sample.c
create mode 100644 target-arc/Makefile.objs
create mode 100644 target-arc/cpu-qom.h
create mode 100644 target-arc/cpu.c
create mode 100644 target-arc/cpu.h
create mode 100644 target-arc/decode.c
create mode 100644 target-arc/gdbstub.c
create mode 100644 target-arc/helper.c
create mode 100644 target-arc/helper.h
create mode 100644 target-arc/machine.c
create mode 100644 target-arc/machine.h
create mode 100644 target-arc/op_helper.c
create mode 100644 target-arc/translate-inst.c
create mode 100644 target-arc/translate-inst.h
create mode 100644 target-arc/translate.c
create mode 100644 target-arc/translate.h
--
2.4.9 (Apple Git-60)
- [Qemu-devel] [PATCH RFC v1 00/29] ARC cores,
Michael Rolnik <=
- [Qemu-devel] [PATCH RFC v1 02/29] target-arc: ADC, ADD, ADD1, ADD2, ADD3, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 04/29] target-arc: AND, OR, XOR, BIC, TST, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 03/29] target-arc: SUB, SUB1, SUB2, SUB3, SBC, RSUB, CMP, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 09/29] target-arc: NEG, ABS, NOT, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 07/29] target-arc: MAX, MIN, Michael Rolnik, 2016/09/08