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[Qemu-devel] [PULL v5 07/18] tcg/arm: Add support for fence
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL v5 07/18] tcg/arm: Add support for fence |
Date: |
Wed, 14 Sep 2016 09:20:02 -0700 |
From: Pranith Kumar <address@hidden>
Cc: Andrzej Zaborowski <address@hidden>
Cc: Peter Maydell <address@hidden>
Signed-off-by: Pranith Kumar <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/arm/tcg-target.inc.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c
index 094f3f8..ffa0d40 100644
--- a/tcg/arm/tcg-target.inc.c
+++ b/tcg/arm/tcg-target.inc.c
@@ -313,6 +313,10 @@ typedef enum {
INSN_LDRD_REG = 0x000000d0,
INSN_STRD_IMM = 0x004000f0,
INSN_STRD_REG = 0x000000f0,
+
+ INSN_DMB_ISH = 0x5bf07ff5,
+ INSN_DMB_MCR = 0xba0f07ee,
+
} ARMInsn;
#define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00)
@@ -1066,6 +1070,15 @@ static inline void tcg_out_goto_label(TCGContext *s, int
cond, TCGLabel *l)
}
}
+static inline void tcg_out_mb(TCGContext *s, TCGArg a0)
+{
+ if (use_armv7_instructions) {
+ tcg_out32(s, INSN_DMB_ISH);
+ } else if (use_armv6_instructions) {
+ tcg_out32(s, INSN_DMB_MCR);
+ }
+}
+
#ifdef CONFIG_SOFTMMU
/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
* int mmu_idx, uintptr_t ra)
@@ -1928,6 +1941,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode
opc,
tcg_out_udiv(s, COND_AL, args[0], args[1], args[2]);
break;
+ case INDEX_op_mb:
+ tcg_out_mb(s, args[0]);
+ break;
+
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
case INDEX_op_call: /* Always emitted via tcg_out_call. */
@@ -2002,6 +2019,7 @@ static const TCGTargetOpDef arm_op_defs[] = {
{ INDEX_op_div_i32, { "r", "r", "r" } },
{ INDEX_op_divu_i32, { "r", "r", "r" } },
+ { INDEX_op_mb, { } },
{ -1 },
};
--
2.7.4
- [Qemu-devel] [PULL v5 00/18] tcg queued patches, Richard Henderson, 2016/09/14
- [Qemu-devel] [PULL v5 03/18] cpu-exec: Check -dfilter for -d cpu, Richard Henderson, 2016/09/14
- [Qemu-devel] [PULL v5 01/18] tcg: Support arbitrary size + alignment, Richard Henderson, 2016/09/14
- [Qemu-devel] [PULL v5 04/18] Introduce TCGOpcode for memory barrier, Richard Henderson, 2016/09/14
- [Qemu-devel] [PULL v5 02/18] tcg: Merge GETPC and GETRA, Richard Henderson, 2016/09/14
- [Qemu-devel] [PULL v5 05/18] tcg/i386: Add support for fence, Richard Henderson, 2016/09/14
- [Qemu-devel] [PULL v5 06/18] tcg/aarch64: Add support for fence, Richard Henderson, 2016/09/14
- [Qemu-devel] [PULL v5 07/18] tcg/arm: Add support for fence,
Richard Henderson <=
- [Qemu-devel] [PULL v5 08/18] tcg/ia64: Add support for fence, Richard Henderson, 2016/09/14
- [Qemu-devel] [PULL v5 10/18] tcg/ppc: Add support for fence, Richard Henderson, 2016/09/14
- [Qemu-devel] [PULL v5 11/18] tcg/s390: Add support for fence, Richard Henderson, 2016/09/14
- [Qemu-devel] [PULL v5 09/18] tcg/mips: Add support for fence, Richard Henderson, 2016/09/14
- [Qemu-devel] [PULL v5 13/18] tcg/tci: Add support for fence, Richard Henderson, 2016/09/14
- [Qemu-devel] [PULL v5 15/18] target-arm: Generate fences in ARMv7 frontend, Richard Henderson, 2016/09/14
- [Qemu-devel] [PULL v5 12/18] tcg/sparc: Add support for fence, Richard Henderson, 2016/09/14
- [Qemu-devel] [PULL v5 14/18] target-alpha: Generate fence op, Richard Henderson, 2016/09/14
- [Qemu-devel] [PULL v5 16/18] target-aarch64: Generate fences for aarch64, Richard Henderson, 2016/09/14
- [Qemu-devel] [PULL v5 17/18] target-i386: Generate fences for x86, Richard Henderson, 2016/09/14