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[Qemu-devel] [PULL 01/36] arm: add Cortex A7 CPU parameters
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 01/36] arm: add Cortex A7 CPU parameters |
Date: |
Thu, 22 Sep 2016 18:21:40 +0100 |
From: Andrey Yurovsky <address@hidden>
Add the "cortex-a7" CPU with features and registers matching the Cortex-A7
MPCore Technical Reference Manual and the Cortex-A7 Floating-Point Unit
Technical Reference Manual. The A7 is very similar to the A15.
Signed-off-by: Andrey Yurovsky <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/cpu.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 46 insertions(+)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index ce8b8f4..1b9540e 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -1129,6 +1129,51 @@ static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
REGINFO_SENTINEL
};
+static void cortex_a7_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ cpu->dtb_compatible = "arm,cortex-a7";
+ set_feature(&cpu->env, ARM_FEATURE_V7);
+ set_feature(&cpu->env, ARM_FEATURE_VFP4);
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
+ set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
+ set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+ set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
+ set_feature(&cpu->env, ARM_FEATURE_LPAE);
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
+ cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7;
+ cpu->midr = 0x410fc075;
+ cpu->reset_fpsid = 0x41023075;
+ cpu->mvfr0 = 0x10110222;
+ cpu->mvfr1 = 0x11111111;
+ cpu->ctr = 0x84448003;
+ cpu->reset_sctlr = 0x00c50078;
+ cpu->id_pfr0 = 0x00001131;
+ cpu->id_pfr1 = 0x00011011;
+ cpu->id_dfr0 = 0x02010555;
+ cpu->pmceid0 = 0x00000000;
+ cpu->pmceid1 = 0x00000000;
+ cpu->id_afr0 = 0x00000000;
+ cpu->id_mmfr0 = 0x10101105;
+ cpu->id_mmfr1 = 0x40000000;
+ cpu->id_mmfr2 = 0x01240000;
+ cpu->id_mmfr3 = 0x02102211;
+ cpu->id_isar0 = 0x01101110;
+ cpu->id_isar1 = 0x13112111;
+ cpu->id_isar2 = 0x21232041;
+ cpu->id_isar3 = 0x11112131;
+ cpu->id_isar4 = 0x10011142;
+ cpu->dbgdidr = 0x3515f005;
+ cpu->clidr = 0x0a200023;
+ cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
+ cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
+ cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
+ define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */
+}
+
static void cortex_a15_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
@@ -1385,6 +1430,7 @@ static const ARMCPUInfo arm_cpus[] = {
{ .name = "cortex-m4", .initfn = cortex_m4_initfn,
.class_init = arm_v7m_class_init },
{ .name = "cortex-r5", .initfn = cortex_r5_initfn },
+ { .name = "cortex-a7", .initfn = cortex_a7_initfn },
{ .name = "cortex-a8", .initfn = cortex_a8_initfn },
{ .name = "cortex-a9", .initfn = cortex_a9_initfn },
{ .name = "cortex-a15", .initfn = cortex_a15_initfn },
--
2.7.4
- [Qemu-devel] [PULL 22/36] cadence_gem: Add support for screening, (continued)
- [Qemu-devel] [PULL 22/36] cadence_gem: Add support for screening, Peter Maydell, 2016/09/22
- [Qemu-devel] [PULL 25/36] xlnx-zynqmp: Set the number of priority queues, Peter Maydell, 2016/09/22
- [Qemu-devel] [PULL 11/36] palmetto-bmc: remove extra no_sdcard assignement, Peter Maydell, 2016/09/22
- [Qemu-devel] [PULL 14/36] aspeed: add a ram_size property to the memory controller, Peter Maydell, 2016/09/22
- [Qemu-devel] [PULL 21/36] cadence_gem: Add the num-priority-queues property, Peter Maydell, 2016/09/22
- [Qemu-devel] [PULL 27/36] loader: Use the specified MemoryRegion, Peter Maydell, 2016/09/22
- [Qemu-devel] [PULL 02/36] ast2400: rename the Aspeed SoC files to aspeed_soc, Peter Maydell, 2016/09/22
- [Qemu-devel] [PULL 20/36] cadence_gem: QOMify Cadence GEM, Peter Maydell, 2016/09/22
- [Qemu-devel] [PULL 29/36] loader: Add AddressSpace loading support to ELFs, Peter Maydell, 2016/09/22
- [Qemu-devel] [PULL 30/36] loader: Add AddressSpace loading support to uImages, Peter Maydell, 2016/09/22
- [Qemu-devel] [PULL 01/36] arm: add Cortex A7 CPU parameters,
Peter Maydell <=
- [Qemu-devel] [PULL 04/36] aspeed-soc: provide a framework to add new SoCs, Peter Maydell, 2016/09/22
- [Qemu-devel] [PULL 31/36] loader: Add AddressSpace loading support to targphys, Peter Maydell, 2016/09/22
- [Qemu-devel] [PULL 32/36] dma: xlnx-zynq-devcfg: Fix up XLNX_ZYNQ_DEVCFG_R_MAX, Peter Maydell, 2016/09/22
- [Qemu-devel] [PULL 34/36] vmstateify ssi-sd, Peter Maydell, 2016/09/22
- [Qemu-devel] [PULL 36/36] imx: Use 'const char', not 'char const', Peter Maydell, 2016/09/22
- [Qemu-devel] [PULL 06/36] palmetto-bmc: replace palmetto_bmc with aspeed, Peter Maydell, 2016/09/22
- [Qemu-devel] [PULL 17/36] hw/ptimer: Introduce timer policy feature, Peter Maydell, 2016/09/22
- [Qemu-devel] [PULL 19/36] tests: Add ptimer tests, Peter Maydell, 2016/09/22
- [Qemu-devel] [PULL 24/36] cadence_gem: Correct indentation, Peter Maydell, 2016/09/22
- [Qemu-devel] [PULL 28/36] loader: Allow a custom AddressSpace when loading ROMs, Peter Maydell, 2016/09/22