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[Qemu-devel] [PULL 07/45] target-ppc: add vector permute right indexed i
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 07/45] target-ppc: add vector permute right indexed instruction |
Date: |
Fri, 23 Sep 2016 17:14:43 +1000 |
From: Rajalakshmi Srinivasaraghavan <address@hidden>
Add vpermr instruction from ISA 3.0.
Signed-off-by: Rajalakshmi Srinivasaraghavan <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 23 +++++++++++++++++++++++
target-ppc/translate/vmx-impl.inc.c | 18 ++++++++++++++++++
target-ppc/translate/vmx-ops.inc.c | 1 +
4 files changed, 43 insertions(+)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index e148861..e75d070 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -270,6 +270,7 @@ DEF_HELPER_5(vmsumubm, void, env, avr, avr, avr, avr)
DEF_HELPER_5(vmsummbm, void, env, avr, avr, avr, avr)
DEF_HELPER_5(vsel, void, env, avr, avr, avr, avr)
DEF_HELPER_5(vperm, void, env, avr, avr, avr, avr)
+DEF_HELPER_5(vpermr, void, env, avr, avr, avr, avr)
DEF_HELPER_4(vpkshss, void, env, avr, avr, avr)
DEF_HELPER_4(vpkshus, void, env, avr, avr, avr)
DEF_HELPER_4(vpkswss, void, env, avr, avr, avr)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index b12af95..291fba0 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -1126,6 +1126,29 @@ void helper_vperm(CPUPPCState *env, ppc_avr_t *r,
ppc_avr_t *a, ppc_avr_t *b,
*r = result;
}
+void helper_vpermr(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b,
+ ppc_avr_t *c)
+{
+ ppc_avr_t result;
+ int i;
+
+ VECTOR_FOR_INORDER_I(i, u8) {
+ int s = c->u8[i] & 0x1f;
+#if defined(HOST_WORDS_BIGENDIAN)
+ int index = 15 - (s & 0xf);
+#else
+ int index = s & 0xf;
+#endif
+
+ if (s & 0x10) {
+ result.u8[i] = a->u8[index];
+ } else {
+ result.u8[i] = b->u8[index];
+ }
+ }
+ *r = result;
+}
+
#if defined(HOST_WORDS_BIGENDIAN)
#define VBPERMQ_INDEX(avr, i) ((avr)->u8[(i)])
#define VBPERMD_INDEX(i) (i)
diff --git a/target-ppc/translate/vmx-impl.inc.c
b/target-ppc/translate/vmx-impl.inc.c
index cb89330..024faf7 100644
--- a/target-ppc/translate/vmx-impl.inc.c
+++ b/target-ppc/translate/vmx-impl.inc.c
@@ -766,6 +766,24 @@ static void gen_vmladduhm(DisasContext *ctx)
tcg_temp_free_ptr(rd);
}
+static void gen_vpermr(DisasContext *ctx)
+{
+ TCGv_ptr ra, rb, rc, rd;
+ if (unlikely(!ctx->altivec_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VPU);
+ return;
+ }
+ ra = gen_avr_ptr(rA(ctx->opcode));
+ rb = gen_avr_ptr(rB(ctx->opcode));
+ rc = gen_avr_ptr(rC(ctx->opcode));
+ rd = gen_avr_ptr(rD(ctx->opcode));
+ gen_helper_vpermr(cpu_env, rd, ra, rb, rc);
+ tcg_temp_free_ptr(ra);
+ tcg_temp_free_ptr(rb);
+ tcg_temp_free_ptr(rc);
+ tcg_temp_free_ptr(rd);
+}
+
GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
diff --git a/target-ppc/translate/vmx-ops.inc.c
b/target-ppc/translate/vmx-ops.inc.c
index a944671..a7022a0 100644
--- a/target-ppc/translate/vmx-ops.inc.c
+++ b/target-ppc/translate/vmx-ops.inc.c
@@ -219,6 +219,7 @@ GEN_VXFORM_300_EO(vctzb, 0x01, 0x18, 0x1C),
GEN_VXFORM_300_EO(vctzh, 0x01, 0x18, 0x1D),
GEN_VXFORM_300_EO(vctzw, 0x01, 0x18, 0x1E),
GEN_VXFORM_300_EO(vctzd, 0x01, 0x18, 0x1F),
+GEN_VXFORM_300(vpermr, 0x1D, 0xFF),
#define GEN_VXFORM_NOA(name, opc2, opc3) \
GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
--
2.7.4
- [Qemu-devel] [PULL 18/45] spapr_rtas: convert to trace framework instead of DPRINTF, (continued)
- [Qemu-devel] [PULL 18/45] spapr_rtas: convert to trace framework instead of DPRINTF, David Gibson, 2016/09/23
- [Qemu-devel] [PULL 21/45] spapr_vscsi: convert to trace framework instead of DPRINTF, David Gibson, 2016/09/23
- [Qemu-devel] [PULL 24/45] target-ppc: convert ld[16, 32, 64]ur to use new macro, David Gibson, 2016/09/23
- [Qemu-devel] [PULL 22/45] target-ppc: consolidate load operations, David Gibson, 2016/09/23
- [Qemu-devel] [PULL 23/45] target-ppc: convert ld64 to use new macro, David Gibson, 2016/09/23
- [Qemu-devel] [PULL 29/45] target-ppc: move out stqcx impementation, David Gibson, 2016/09/23
- [Qemu-devel] [PULL 28/45] target-ppc: consolidate load with reservation, David Gibson, 2016/09/23
- [Qemu-devel] [PULL 27/45] target-ppc: convert st[16, 32, 64]r to use new macro, David Gibson, 2016/09/23
- [Qemu-devel] [PULL 31/45] target-ppc: add xxspltib instruction, David Gibson, 2016/09/23
- [Qemu-devel] [PULL 30/45] target-ppc: consolidate store conditional, David Gibson, 2016/09/23
- [Qemu-devel] [PULL 07/45] target-ppc: add vector permute right indexed instruction,
David Gibson <=
- [Qemu-devel] [PULL 33/45] target-ppc: add stxsi[bh]x instruction, David Gibson, 2016/09/23
- [Qemu-devel] [PULL 36/45] target-ppc: add TLB_NEED_LOCAL_FLUSH flag, David Gibson, 2016/09/23
- [Qemu-devel] [PULL 35/45] spapr: Introduce sPAPRCPUCoreClass, David Gibson, 2016/09/23
- [Qemu-devel] [PULL 26/45] target-ppc: convert st64 to use new macro, David Gibson, 2016/09/23
- [Qemu-devel] [PULL 42/45] ppc/kvm: Mark 64kB page size support as disabled if not available, David Gibson, 2016/09/23
- [Qemu-devel] [PULL 32/45] target-ppc: add lxsi[bw]zx instruction, David Gibson, 2016/09/23
- [Qemu-devel] [PULL 43/45] linux-user: ppc64: fix ARCH_206 bit in AT_HWCAP, David Gibson, 2016/09/23
- [Qemu-devel] [PULL 40/45] ppc/xics: account correct irq status, David Gibson, 2016/09/23
- [Qemu-devel] [PULL 06/45] target-ppc: add vector bit permute doubleword instruction, David Gibson, 2016/09/23
- [Qemu-devel] [PULL 08/45] ppc: Fix signal delivery in ppc-user and ppc64-user, David Gibson, 2016/09/23