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[Qemu-devel] [PULL 25/45] target-ppc: consolidate store operations
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 25/45] target-ppc: consolidate store operations |
Date: |
Fri, 23 Sep 2016 17:15:01 +1000 |
From: Nikunj A Dadhania <address@hidden>
Implement macro to consolidate store operations using newer
tcg_gen_qemu_st function.
Signed-off-by: Nikunj A Dadhania <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target-ppc/translate.c | 35 ++++++++++++++++-------------------
1 file changed, 16 insertions(+), 19 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 0d27067..f228ae0 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -2498,30 +2498,27 @@ GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q))
GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q))
#endif
-static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
-{
- tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
+#define GEN_QEMU_STORE_TL(stop, op) \
+static void glue(gen_qemu_, stop)(DisasContext *ctx, \
+ TCGv val, \
+ TCGv addr) \
+{ \
+ tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \
}
-static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
-{
- TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
- tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
-}
+GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB))
+GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW))
+GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL))
-static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
-{
- TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
- tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
+#define GEN_QEMU_STORE_64(stop, op) \
+static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \
+ TCGv_i64 val, \
+ TCGv addr) \
+{ \
+ tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \
}
-static void gen_qemu_st32_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
-{
- TCGv tmp = tcg_temp_new();
- tcg_gen_trunc_i64_tl(tmp, val);
- gen_qemu_st32(ctx, tmp, addr);
- tcg_temp_free(tmp);
-}
+GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL))
static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
{
--
2.7.4
- [Qemu-devel] [PULL 43/45] linux-user: ppc64: fix ARCH_206 bit in AT_HWCAP, (continued)
- [Qemu-devel] [PULL 43/45] linux-user: ppc64: fix ARCH_206 bit in AT_HWCAP, David Gibson, 2016/09/23
- [Qemu-devel] [PULL 40/45] ppc/xics: account correct irq status, David Gibson, 2016/09/23
- [Qemu-devel] [PULL 06/45] target-ppc: add vector bit permute doubleword instruction, David Gibson, 2016/09/23
- [Qemu-devel] [PULL 08/45] ppc: Fix signal delivery in ppc-user and ppc64-user, David Gibson, 2016/09/23
- [Qemu-devel] [PULL 14/45] adb.c: add support for QKeyCode, David Gibson, 2016/09/23
- [Qemu-devel] [PULL 34/45] target-ppc: implement darn instruction, David Gibson, 2016/09/23
- [Qemu-devel] [PULL 39/45] Enable H_CLEAR_MOD and H_CLEAR_REF hypercalls on KVM/PPC64., David Gibson, 2016/09/23
- [Qemu-devel] [PULL 38/45] target-ppc: tlbie/tlbivax should have global effect, David Gibson, 2016/09/23
- [Qemu-devel] [PULL 10/45] libqos: define SPAPR libqos functions, David Gibson, 2016/09/23
- [Qemu-devel] [PULL 41/45] ppc/xics: An ICS with offset 0 is assumed to be uninitialized, David Gibson, 2016/09/23
- [Qemu-devel] [PULL 25/45] target-ppc: consolidate store operations,
David Gibson <=
- [Qemu-devel] [PULL 45/45] spapr_pci: Add numa node id, David Gibson, 2016/09/23
- [Qemu-devel] [PULL 05/45] target-ppc: add vector count trailing zeros instructions, David Gibson, 2016/09/23
- [Qemu-devel] [PULL 37/45] target-ppc: add flag in check_tlb_flush(), David Gibson, 2016/09/23
- [Qemu-devel] [PULL 44/45] monitor: fix crash for platforms without a CPU 0, David Gibson, 2016/09/23
- [Qemu-devel] [PULL 11/45] tests: add RTAS command in the protocol, David Gibson, 2016/09/23
- Re: [Qemu-devel] [PULL 00/45] ppc-for-2.8 queue 20160923, no-reply, 2016/09/23
- Re: [Qemu-devel] [PULL 00/45] ppc-for-2.8 queue 20160923, Peter Maydell, 2016/09/23