[Qemu-devel] [PATCH 01/18] target-riscv: Add RISC-V target stubs and Maintainer

[Sagar Karandikar]

Only files that live outside of target-riscv and hw/riscv, excluding
configure and default-configs changes.

Signed-off-by: Sagar Karandikar <address@hidden>
---
 MAINTAINERS                |  7 +++++++
 arch_init.c                |  2 ++
 cpus.c                     |  6 ++++++
 include/elf.h              |  2 ++
 include/sysemu/arch_init.h |  1 +
 qapi-schema.json           | 14 +++++++++++++-
 6 files changed, 31 insertions(+), 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index a3a2ad7..dbbbe0f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -175,6 +175,13 @@ F: hw/ppc/
 F: include/hw/ppc/
 F: disas/ppc.c
 
+RISC-V
+M: Sagar Karandikar <address@hidden>
+M: Bastian Koppelmann <address@hidden>
+S: Maintained
+F: target-riscv/
+F: hw/riscv/
+
 S390
 M: Richard Henderson <address@hidden>
 M: Alexander Graf <address@hidden>
diff --git a/arch_init.c b/arch_init.c
index 5cc58b2..c89c45d 100644
--- a/arch_init.c
+++ b/arch_init.c
@@ -62,6 +62,8 @@ int graphic_depth = 32;
 #define QEMU_ARCH QEMU_ARCH_MICROBLAZE
 #elif defined(TARGET_MIPS)
 #define QEMU_ARCH QEMU_ARCH_MIPS
+#elif defined(TARGET_RISCV)
+#define QEMU_ARCH QEMU_ARCH_RISCV
 #elif defined(TARGET_MOXIE)
 #define QEMU_ARCH QEMU_ARCH_MOXIE
 #elif defined(TARGET_OPENRISC)
diff --git a/cpus.c b/cpus.c
index e39ccb7..41ccc29 100644
--- a/cpus.c
+++ b/cpus.c
@@ -1618,6 +1618,9 @@ CpuInfoList *qmp_query_cpus(Error **errp)
 #elif defined(TARGET_SPARC)
         SPARCCPU *sparc_cpu = SPARC_CPU(cpu);
         CPUSPARCState *env = &sparc_cpu->env;
+#elif defined(TARGET_RISCV)
+        RISCVCPU *riscv_cpu = RISCV_CPU(cpu);
+        CPURISCVState *env = &riscv_cpu->env;
 #elif defined(TARGET_MIPS)
         MIPSCPU *mips_cpu = MIPS_CPU(cpu);
         CPUMIPSState *env = &mips_cpu->env;
@@ -1651,6 +1654,9 @@ CpuInfoList *qmp_query_cpus(Error **errp)
 #elif defined(TARGET_TRICORE)
         info->value->arch = CPU_INFO_ARCH_TRICORE;
         info->value->u.tricore.PC = env->PC;
+#elif defined(TARGET_RISCV)
+        info->value->arch = CPU_INFO_ARCH_RISCV;
+        info->value->u.riscv.pc = env->PC;
 #else
         info->value->arch = CPU_INFO_ARCH_OTHER;
 #endif
diff --git a/include/elf.h b/include/elf.h
index 1c2975d..1221359 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -112,6 +112,8 @@ typedef int64_t  Elf64_Sxword;
 
 #define EM_UNICORE32    110     /* UniCore32 */
 
+#define EM_RISCV 243 /* RISC-V */
+
 /*
  * This is an interim value that we will use until the committee comes
  * up with a final number.
diff --git a/include/sysemu/arch_init.h b/include/sysemu/arch_init.h
index 1c9dad1..8684aac 100644
--- a/include/sysemu/arch_init.h
+++ b/include/sysemu/arch_init.h
@@ -23,6 +23,7 @@ enum {
     QEMU_ARCH_UNICORE32 = (1 << 14),
     QEMU_ARCH_MOXIE = (1 << 15),
     QEMU_ARCH_TRICORE = (1 << 16),
+    QEMU_ARCH_RISCV = (1 << 17),
 };
 
 extern const uint32_t arch_type;
diff --git a/qapi-schema.json b/qapi-schema.json
index e507061..11cd848 100644
--- a/qapi-schema.json
+++ b/qapi-schema.json
@@ -832,7 +832,7 @@
 # Since: 2.6
 ##
 { 'enum': 'CpuInfoArch',
-  'data': ['x86', 'sparc', 'ppc', 'mips', 'tricore', 'other' ] }
+  'data': ['x86', 'sparc', 'ppc', 'mips', 'tricore', 'riscv', 'other' ] }
 
 ##
 # @CpuInfo:
@@ -867,6 +867,7 @@
             'ppc': 'CpuInfoPPC',
             'mips': 'CpuInfoMIPS',
             'tricore': 'CpuInfoTricore',
+            'riscv': 'CpuInfoRISCV',
             'other': 'CpuInfoOther' } }
 
 ##
@@ -927,6 +928,17 @@
 { 'struct': 'CpuInfoTricore', 'data': { 'PC': 'int' } }
 
 ##
+# @CpuInfoRISCV:
+#
+# Additional information about a virtual RISCV CPU
+#
+# @PC: the instruction pointer
+#
+# Since 2.6
+##
+{ 'struct': 'CpuInfoRISCV', 'data': { 'pc': 'int' } }
+
+##
 # @CpuInfoOther:
 #
 # No additional information is available about the virtual CPU
-- 
2.9.3