Re: [Qemu-devel] [PATCH 11/18] target-riscv: Add Double Precision Floating-Point Instructions

[Richard Henderson]

On 09/26/2016 03:56 AM, Sagar Karandikar wrote:
> +    case OPC_RISC_FSGNJ_D:
> +        /* also OPC_RISC_FSGNJN_D, OPC_RISC_FSGNJX_D */
> +        if (rm == 0x0) {
> +            gen_helper_fsgnj_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
> +                               cpu_fpr[rs2]);
> +        } else if (rm == 0x1) {
> +            gen_helper_fsgnjn_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
> +                                cpu_fpr[rs2]);
> +        } else if (rm == 0x2) {
> +            gen_helper_fsgnjx_d(cpu_fpr[rd], cpu_env, cpu_fpr[rs1],
> +                                cpu_fpr[rs2]);
> +        } else {
> +            kill_unknown(ctx, RISCV_EXCP_ILLEGAL_INST);
> +        }

I forgot to mention this for single-precision -- given that FMOV is an alias of 
FSGNJ, you should special case rs1 == rs2.


r~