Re: [Qemu-devel] [PATCH 12/18] target-riscv: Add system instructions

[Richard Henderson]

On 09/26/2016 03:56 AM, Sagar Karandikar wrote:
> +void helper_fence_i(CPURISCVState *env)
> +{
> +    RISCVCPU *cpu = riscv_env_get_cpu(env);
> +    CPUState *cs = CPU(cpu);
> +    /* Flush QEMU's TLB */
> +    tlb_flush(cs, 1);
> +    /* ARM port seems to not know if this is okay inside a TB
> +       But we need to do it */
> +    tb_flush(cs);
> +}

You should not need to tb_flush for fence_i.  QEMU's internals auto-detect when 
a memory write invalidates a TB.


r~