Re: [Qemu-devel] [PATCH 09/18] target-riscv: Add FMADD, FMSUB, FNMADD, FNMSUB Instructions,

[Richard Henderson]

On 09/26/2016 03:56 AM, Sagar Karandikar wrote:
> +/* adapted from Spike's decode.h:set_fp_exceptions */
> +#define set_fp_exceptions() do { \
> +    env->csr[CSR_FFLAGS] |= 
> softfloat_flags_to_riscv(get_float_exception_flags(\
> +                            &env->fp_status)); \
> +    set_float_exception_flags(0, &env->fp_status); \
> +} while (0)
> +
> +uint64_t helper_fmadd_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
> +                        uint64_t frs3, uint64_t rm)
> +{
> +    set_float_rounding_mode(RM, &env->fp_status);
> +    frs1 = float32_muladd(frs1, frs2, frs3, 0, &env->fp_status);
> +    set_fp_exceptions();
> +    return frs1;
> +}

I should also mention that I think it would be preferable to canonically store
the fflags csr in fp_status.  This means that you only need to perform this
flags conversion when reading or writing the csr, and not upon every fp insn.

The conversion of bits at each fp insn is done on other targets in order to
notice when exceptions must be taken.  Since riscv has no fp exceptions, this
isn't a factor.


r~