Re: [Qemu-devel] [PATCH 08/18] target-riscv: Add Atomic Instructions

[Richard Henderson]

On 09/26/2016 03:56 AM, Sagar Karandikar wrote:
> +static inline void gen_atomic(DisasContext *ctx, uint32_t opc,
> +                      int rd, int rs1, int rs2)
> +{
> +    /* TODO: handle aq, rl bits? - for now just get rid of them: */
> +    opc = MASK_OP_ATOMIC_NO_AQ_RL(opc);

We have already added tcg_gen_mb to insert memory barriers; hopefully the
branch containing atomic operations will be merged soon.  See

  git://github.com/rth7680/qemu.git atomic-4


> +    case OPC_RISC_SC_W:
> +        tcg_gen_brcond_tl(TCG_COND_NE, load_res, source1, j);
> +        tcg_gen_qemu_st_tl(source2, source1, ctx->mem_idx, MO_TEUL | 
> MO_ALIGN);
> +        tcg_gen_movi_tl(dat, 0); /*success */
> +        tcg_gen_br(done);
> +        gen_set_label(j);
> +        tcg_gen_movi_tl(dat, 1); /*fail */
> +        gen_set_label(done);
> +        break;

I will note that generally SC needs to compare against the value loaded by LR
as well as the address used by LR.  Please have a look at the AArch64
implementation.


r~