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Re: [Qemu-devel] [PATCH 8/9] target-cris: add v17 CPU
From: |
Edgar E. Iglesias |
Subject: |
Re: [Qemu-devel] [PATCH 8/9] target-cris: add v17 CPU |
Date: |
Wed, 28 Sep 2016 12:42:41 +0200 |
User-agent: |
Mutt/1.5.24 (2015-08-30) |
On Mon, Sep 26, 2016 at 09:17:33AM +0200, Rabin Vincent wrote:
> On Tue, Sep 13, 2016 at 12:18:00AM +0200, Edgar E. Iglesias wrote:
> > On Mon, Sep 05, 2016 at 01:54:11PM +0200, Rabin Vincent wrote:
> > > diff --git a/target-cris/translate_v10.c b/target-cris/translate_v10.c
> > > index a3da425..33d86eb 100644
> > > --- a/target-cris/translate_v10.c
> > > +++ b/target-cris/translate_v10.c
> > > @@ -1097,6 +1097,14 @@ static unsigned int dec10_ind(CPUCRISState *env,
> > > DisasContext *dc)
> > > insn_len = dec10_bdap_m(env, dc, size);
> > > break;
> > > default:
> > > + if (dc->opcode == CRISV17_IND_ADDC && dc->size == 2 &&
> > > + env->pregs[PR_VR] == 17) {
> >
> > Could you please add some comments on the insn encoding?
> > Put the stuff from the commit msg in here.
>
> OK, see new patch below.
>
> > IIRC, ADDC and v17 are modifications made to the CRISv10 family of
> > cores that never made it into the public manuals. Or am I wrong?
Thanks Rabin,
I've applied these except patch #7 "ignore prefix insns in singlestep".
Patch #8 had an issue with checkpatch that I fixed up.
Cheers,
Edgar
>
> No, you're right.
>
> 8<---------------
> From 513465ad3f007885bafba3482705ba57cacd588b Mon Sep 17 00:00:00 2001
> From: Rabin Vincent <address@hidden>
> Date: Mon, 15 Aug 2016 13:59:32 +0200
> Subject: [PATCH] target-cris: add v17 CPU
>
> In the CRIS v17 CPU an ADDC (add with carry) instruction has been added
> compared to the v10 instruction set.
>
> Assembler syntax:
>
> ADDC [Rs],Rd
> ADDC [Rs+],Rd
>
> Size: Dword
>
> Description:
>
> The source data is added together with the carry flag to the
> destination register. The size of the operation is dword.
>
> Operation:
>
> Rd += s + C-flag;
>
> Flags affected:
>
> S R P U I X N Z V C
> - - - - - 0 * * * *
>
> Instruction format: ADDC [Rs],Rd
>
> +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
> |Destination(Rd)| 1 0 0 1 1 0 1 0 | Source(Rs) |
> +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
>
> Instruction format: ADDC [Rs+],Rd
>
> +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
> |Destination(Rd)| 1 1 0 1 1 0 1 0 | Source(Rs) |
> +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
>
> Signed-off-by: Rabin Vincent <address@hidden>
> ---
> target-cris/cpu.c | 14 ++++++++++++++
> target-cris/crisv10-decode.h | 1 +
> target-cris/translate_v10.c | 23 +++++++++++++++++++++++
> 3 files changed, 38 insertions(+)
>
> diff --git a/target-cris/cpu.c b/target-cris/cpu.c
> index c5a656b..d680cfb 100644
> --- a/target-cris/cpu.c
> +++ b/target-cris/cpu.c
> @@ -246,6 +246,16 @@ static void crisv11_cpu_class_init(ObjectClass *oc, void
> *data)
> cc->gdb_read_register = crisv10_cpu_gdb_read_register;
> }
>
> +static void crisv17_cpu_class_init(ObjectClass *oc, void *data)
> +{
> + CPUClass *cc = CPU_CLASS(oc);
> + CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
> +
> + ccc->vr = 17;
> + cc->do_interrupt = crisv10_cpu_do_interrupt;
> + cc->gdb_read_register = crisv10_cpu_gdb_read_register;
> +}
> +
> static void crisv32_cpu_class_init(ObjectClass *oc, void *data)
> {
> CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
> @@ -273,6 +283,10 @@ static const TypeInfo cris_cpu_model_type_infos[] = {
> .parent = TYPE_CRIS_CPU,
> .class_init = crisv11_cpu_class_init,
> }, {
> + .name = TYPE("crisv17"),
> + .parent = TYPE_CRIS_CPU,
> + .class_init = crisv17_cpu_class_init,
> + }, {
> .name = TYPE("crisv32"),
> .parent = TYPE_CRIS_CPU,
> .class_init = crisv32_cpu_class_init,
> diff --git a/target-cris/crisv10-decode.h b/target-cris/crisv10-decode.h
> index 587fbdd..bdb4b6d 100644
> --- a/target-cris/crisv10-decode.h
> +++ b/target-cris/crisv10-decode.h
> @@ -92,6 +92,7 @@
> #define CRISV10_IND_JUMP_M 4
> #define CRISV10_IND_DIP 5
> #define CRISV10_IND_JUMP_R 6
> +#define CRISV17_IND_ADDC 6
> #define CRISV10_IND_BOUND 7
> #define CRISV10_IND_BCC_M 7
> #define CRISV10_IND_MOVE_M_SPR 8
> diff --git a/target-cris/translate_v10.c b/target-cris/translate_v10.c
> index 4707a18..0e4d039 100644
> --- a/target-cris/translate_v10.c
> +++ b/target-cris/translate_v10.c
> @@ -1094,6 +1094,29 @@ static unsigned int dec10_ind(CPUCRISState *env,
> DisasContext *dc)
> insn_len = dec10_bdap_m(env, dc, size);
> break;
> default:
> + /*
> + * ADDC for v17:
> + *
> + * Instruction format: ADDC [Rs],Rd
> + *
> + *
> +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
> + * |Destination(Rd)| 1 0 0 1 1 0 1 0 |
> Source(Rs) |
> + *
> +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
> + *
> + * Instruction format: ADDC [Rs+],Rd
> + *
> + *
> +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
> + * |Destination(Rd)| 1 1 0 1 1 0 1 0 |
> Source(Rs) |
> + *
> +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
> + */
> + if (dc->opcode == CRISV17_IND_ADDC && dc->size == 2 &&
> + env->pregs[PR_VR] == 17) {
> + LOG_DIS("addc op=%d %d\n", dc->src, dc->dst);
> + cris_cc_mask(dc, CC_MASK_NZVC);
> + insn_len += dec10_ind_alu(env, dc, CC_OP_ADDC, size);
> + break;
> + }
> +
> LOG_DIS("pc=%x var-ind.%d %d r%d r%d\n",
> dc->pc, size, dc->opcode, dc->src, dc->dst);
> cpu_abort(CPU(dc->cpu), "Unhandled opcode");
> --
> 2.1.4
>
- [Qemu-devel] [PATCH 3/9] tests: cris: remove openpf4 test, (continued)
[Qemu-devel] [PATCH 2/9] tests: cris: fix syscall inline asm, Rabin Vincent, 2016/09/05
[Qemu-devel] [PATCH 5/9] target-cris: sync CC state at load/stores., Rabin Vincent, 2016/09/05
[Qemu-devel] [PATCH 6/9] target-cris: reduce v32isms from v10 log dumps, Rabin Vincent, 2016/09/05