Re: [Qemu-devel] [PATCH v4 2/9] target-ppc: Implement mtvsrdd instruction

[David Gibson]

On Wed, Sep 28, 2016 at 11:01:20AM +0530, Nikunj A Dadhania wrote:
> From: Ravi Bangoria <address@hidden>
> 
> mtvsrdd: Move To VSR Double Doubleword
> 
> Signed-off-by: Ravi Bangoria <address@hidden>
> Signed-off-by: Nikunj A Dadhania <address@hidden>
> ---
>  target-ppc/translate/vsx-impl.inc.c | 23 +++++++++++++++++++++++
>  target-ppc/translate/vsx-ops.inc.c  |  1 +
>  2 files changed, 24 insertions(+)
> 
> diff --git a/target-ppc/translate/vsx-impl.inc.c 
> b/target-ppc/translate/vsx-impl.inc.c
> index b669e8c..f9db1d4 100644
> --- a/target-ppc/translate/vsx-impl.inc.c
> +++ b/target-ppc/translate/vsx-impl.inc.c
> @@ -234,6 +234,29 @@ static void gen_mfvsrld(DisasContext *ctx)
>      tcg_gen_mov_i64(cpu_gpr[rA(ctx->opcode)], cpu_vsrl(xS(ctx->opcode)));
>  }
>  
> +static void gen_mtvsrdd(DisasContext *ctx)
> +{
> +    if (xT(ctx->opcode) < 32) {
> +        if (unlikely(!ctx->vsx_enabled)) {
> +            gen_exception(ctx, POWERPC_EXCP_VSXU);
> +            return;
> +        }
> +    } else {
> +        if (unlikely(!ctx->altivec_enabled)) {
> +            gen_exception(ctx, POWERPC_EXCP_VPU);
> +            return;
> +        }
> +    }

Huh.. so in the ISA doc version I have at least (p114), the
pseudo-code for the instruction states either vector or VSX
exceptions.  The text however says either FP or vector exceptions.

The pseudo-code version seems more sensible which is what you've
implemented, so I'm guessing this is just an error in the descriptive
text.

It'd be nice to confirm that against real hardware behaviour if
possible though.

> +
> +    if (!rA(ctx->opcode)) {
> +        tcg_gen_movi_i64(cpu_vsrh(xT(ctx->opcode)), 0);
> +    } else {
> +       tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_gpr[rA(ctx->opcode)]);
> +    }
> +
> +    tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_gpr[rB(ctx->opcode)]);
> +}
> +
>  #endif
>  
>  static void gen_xxpermdi(DisasContext *ctx)
> diff --git a/target-ppc/translate/vsx-ops.inc.c 
> b/target-ppc/translate/vsx-ops.inc.c
> index 3b296f8..1287973 100644
> --- a/target-ppc/translate/vsx-ops.inc.c
> +++ b/target-ppc/translate/vsx-ops.inc.c
> @@ -23,6 +23,7 @@ GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, 
> PPC_NONE, PPC2_VSX207),
>  GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207),
>  GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207),
>  GEN_HANDLER_E(mfvsrld, 0X1F, 0x13, 0x09, 0x0000F800, PPC_NONE, PPC2_ISA300),
> +GEN_HANDLER_E(mtvsrdd, 0X1F, 0x13, 0x0D, 0x0, PPC_NONE, PPC2_ISA300),
>  #endif
>  
>  #define GEN_XX1FORM(name, opc2, opc3, fl2)                              \

-- 
David Gibson                    | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au  | minimalist, thank you.  NOT _the_ _other_
                                | _way_ _around_!
http://www.ozlabs.org/~dgibson

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