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Re: [Qemu-devel] [PATCH 09/29] target-sparc: hypervisor mode takes over
From: |
Artyom Tarasenko |
Subject: |
Re: [Qemu-devel] [PATCH 09/29] target-sparc: hypervisor mode takes over nucleus mode |
Date: |
Wed, 12 Oct 2016 13:33:02 +0200 |
On Mon, Oct 10, 2016 at 11:41 PM, Richard Henderson <address@hidden> wrote:
> On 10/01/2016 05:05 AM, Artyom Tarasenko wrote:
>>
>> Signed-off-by: Artyom Tarasenko <address@hidden>
>> ---
>> target-sparc/cpu.h | 6 +++---
>> 1 file changed, 3 insertions(+), 3 deletions(-)
>>
>> diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
>> index 0b5c79f..fbeb8d7 100644
>> --- a/target-sparc/cpu.h
>> +++ b/target-sparc/cpu.h
>> @@ -699,10 +699,10 @@ static inline int cpu_mmu_index(CPUSPARCState *env1,
>> bool ifetch)
>> #elif !defined(TARGET_SPARC64)
>> return env1->psrs;
>> #else
>> - if (env1->tl > 0) {
>> - return MMU_NUCLEUS_IDX;
>> - } else if (cpu_hypervisor_mode(env1)) {
>> + if (cpu_hypervisor_mode(env1)) {
>> return MMU_HYPV_IDX;
>> + } else if (env1->tl > 0) {
>> + return MMU_NUCLEUS_IDX;
>> } else if (cpu_supervisor_mode(env1)) {
>> return MMU_KERNEL_IDX;
>> } else {
>>
>
> While playing with your patch set, I discovered that we also need a patch to
> get_asi for ASI_N et al to retain MMU_HYPV_IDX, and not decrease privilege.
> This happens *very* early in the prom boot, with the first casx (when casx
> is implemented inline).
Why is the bug not visible with the current master? I wonder if we
have a symmetrical bug somewhere.
--
Regards,
Artyom Tarasenko
SPARC and PPC PReP under qemu blog: http://tyom.blogspot.com/search/label/qemu
- [Qemu-devel] [PATCH 06/29] target-sparc: simplify replace_tlb_entry by using TTE_PGSIZE, (continued)
- [Qemu-devel] [PATCH 06/29] target-sparc: simplify replace_tlb_entry by using TTE_PGSIZE, Artyom Tarasenko, 2016/10/01
- [Qemu-devel] [PATCH 05/29] target-sparc: on UA2005 don't deliver Interrupt_level_n IRQs in hypervisor mode, Artyom Tarasenko, 2016/10/01
- [Qemu-devel] [PATCH 08/29] target-sparc: implement UltraSPARC-T1 Strand status ASR, Artyom Tarasenko, 2016/10/01
- [Qemu-devel] [PATCH 07/29] target-sparc: implement UA2005 scratchpad registers, Artyom Tarasenko, 2016/10/01
- [Qemu-devel] [PATCH 09/29] target-sparc: hypervisor mode takes over nucleus mode, Artyom Tarasenko, 2016/10/01
- [Qemu-devel] [PATCH 11/29] target-sparc: implement UA2005 GL register, Artyom Tarasenko, 2016/10/01
- [Qemu-devel] [PATCH 10/29] target-sparc: implement UA2005 hypervisor traps, Artyom Tarasenko, 2016/10/01
- [Qemu-devel] [PATCH 12/29] target-sparc: implement UA2005 rdhpstate and wrhpstate instructions, Artyom Tarasenko, 2016/10/01
- [Qemu-devel] [PATCH 13/29] target-sparc: fix immediate UA2005 traps, Artyom Tarasenko, 2016/10/01
- [Qemu-devel] [PATCH 14/29] target-sparc: use direct address translation in hyperprivileged mode, Artyom Tarasenko, 2016/10/01