Re: [Qemu-devel] [PATCH 2/2] target-mips: Fix Loongson multimedia instructions.

[Heiher]

On Fri, Oct 14, 2016 at 12:44 AM, Yongbok Kim <address@hidden> wrote:
>
>
> On 13/10/2016 08:10, Heiher wrote:
>> From: Heiher <address@hidden>
>>
>> Needed to emit FPU exception on Loongson multimedia instructions
>> executing if Status:CU1 is clear. or FPR changes may be missed
>> on Linux.
>>
>> Signed-off-by: Heiher <address@hidden>
>> Signed-off-by: Fuxin Zhang <address@hidden>
>> ---
>>  target-mips/translate.c | 1 +
>>  1 file changed, 1 insertion(+)
>>
>> diff --git a/target-mips/translate.c b/target-mips/translate.c
>> index 139f249..b87a09b 100644
>> --- a/target-mips/translate.c
>> +++ b/target-mips/translate.c
>> @@ -3871,6 +3871,7 @@ static void gen_loongson_multimedia(DisasContext *ctx, 
>> int rd, int rs, int rt)
>>          break;
>>      }
>>
>> +    check_cp1_enabled(ctx);
>
> Isn't it also required to check Status.CU2 bit? I guess the Loongson
> Multimedia instructions was implemented as the Cop2? Please correct me if I
> am wrong with this.

I don't think the Loongson CPUs have real coprocessor 2 although these
multimedia instructions are encoding as Cp2. Similar to MSA, these
instructions reusing 64-bit FPRs. In fact, The older Loongson CPUs
emit Cp2 unusable exception, so a cp2 hook is needed to combine FPU
and Cp2 in kernel. In new revision, Cp1 exception is emitted.

>
>>      gen_load_fpr64(ctx, t0, rs);
>>      gen_load_fpr64(ctx, t1, rt);
>>
>>
>
> Regards,
> Yongbok



-- 
Best regards!
Heiher
http://hev.cc