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[Qemu-devel] [PULL 13/21] intel_iommu: pass whole remapped addresses to
From: |
Eduardo Habkost |
Subject: |
[Qemu-devel] [PULL 13/21] intel_iommu: pass whole remapped addresses to apic |
Date: |
Mon, 17 Oct 2016 15:51:30 -0200 |
From: Radim Krčmář <address@hidden>
The MMIO interface to APIC only allowed 8 bit addresses, which is not
enough for 32 bit addresses from EIM remapping.
Intel stored upper 24 bits in the high MSI address, so use the same
technique. The technique is also used in KVM MSI interface.
Other APICs are unlikely to handle those upper bits.
Reviewed-by: Peter Xu <address@hidden>
Signed-off-by: Radim Krčmář <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>
---
hw/i386/intel_iommu.c | 21 +++++++++------------
1 file changed, 9 insertions(+), 12 deletions(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 2efd69b..d22a51c 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -32,6 +32,7 @@
#include "hw/i386/x86-iommu.h"
#include "hw/pci-host/q35.h"
#include "sysemu/kvm.h"
+#include "hw/i386/apic_internal.h"
/*#define DEBUG_INTEL_IOMMU*/
#ifdef DEBUG_INTEL_IOMMU
@@ -280,18 +281,17 @@ static void vtd_update_iotlb(IntelIOMMUState *s, uint16_t
source_id,
static void vtd_generate_interrupt(IntelIOMMUState *s, hwaddr mesg_addr_reg,
hwaddr mesg_data_reg)
{
- hwaddr addr;
- uint32_t data;
+ MSIMessage msi;
assert(mesg_data_reg < DMAR_REG_SIZE);
assert(mesg_addr_reg < DMAR_REG_SIZE);
- addr = vtd_get_long_raw(s, mesg_addr_reg);
- data = vtd_get_long_raw(s, mesg_data_reg);
+ msi.address = vtd_get_long_raw(s, mesg_addr_reg);
+ msi.data = vtd_get_long_raw(s, mesg_data_reg);
- VTD_DPRINTF(FLOG, "msi: addr 0x%"PRIx64 " data 0x%"PRIx32, addr, data);
- address_space_stl_le(&address_space_memory, addr, data,
- MEMTXATTRS_UNSPECIFIED, NULL);
+ VTD_DPRINTF(FLOG, "msi: addr 0x%"PRIx64 " data 0x%"PRIx32,
+ msi.address, msi.data);
+ apic_get_class()->send_msi(&msi);
}
/* Generate a fault event to software via MSI if conditions are met.
@@ -2134,6 +2134,7 @@ static void vtd_generate_msi_message(VTDIrq *irq,
MSIMessage *msg_out)
msg.dest_mode = irq->dest_mode;
msg.redir_hint = irq->redir_hint;
msg.dest = irq->dest;
+ msg.__addr_hi = irq->dest & 0xffffff00;
msg.__addr_head = cpu_to_le32(0xfee);
/* Keep this from original MSI address bits */
msg.__not_used = irq->msi_addr_last_bits;
@@ -2293,11 +2294,7 @@ static MemTxResult vtd_mem_ir_write(void *opaque, hwaddr
addr,
" for device sid 0x%04x",
to.address, to.data, sid);
- if (dma_memory_write(&address_space_memory, to.address,
- &to.data, size)) {
- VTD_DPRINTF(GENERAL, "error: fail to write 0x%"PRIx64
- " value 0x%"PRIx32, to.address, to.data);
- }
+ apic_get_class()->send_msi(&to);
return MEMTX_OK;
}
--
2.7.4
- [Qemu-devel] [PULL 03/21] target-i386: Disable VME by default with TCG, (continued)
- [Qemu-devel] [PULL 03/21] target-i386: Disable VME by default with TCG, Eduardo Habkost, 2016/10/17
- [Qemu-devel] [PULL 04/21] target-i386: Register aliases for feature names with underscores, Eduardo Habkost, 2016/10/17
- [Qemu-devel] [PULL 06/21] target-i386: Remove underscores from feat_names arrays, Eduardo Habkost, 2016/10/17
- [Qemu-devel] [PULL 07/21] target-i386: Register properties for feature aliases manually, Eduardo Habkost, 2016/10/17
- [Qemu-devel] [PULL 05/21] target-i386: Make plus_features/minus_features QOM-based, Eduardo Habkost, 2016/10/17
- [Qemu-devel] [PULL 08/21] target-i386: xsave: Add FP and SSE bits to x86_ext_save_areas, Eduardo Habkost, 2016/10/17
- [Qemu-devel] [PULL 09/21] qmp: Add runnability information to query-cpu-definitions, Eduardo Habkost, 2016/10/17
- [Qemu-devel] [PULL 11/21] apic: add global apic_get_class(), Eduardo Habkost, 2016/10/17
- [Qemu-devel] [PULL 10/21] target-i386: Move warning code outside x86_cpu_filter_features(), Eduardo Habkost, 2016/10/17
- [Qemu-devel] [PULL 12/21] apic: add send_msi() to APICCommonClass, Eduardo Habkost, 2016/10/17
- [Qemu-devel] [PULL 13/21] intel_iommu: pass whole remapped addresses to apic,
Eduardo Habkost <=
- [Qemu-devel] [PULL 14/21] intel_iommu: redo configuraton check in realize, Eduardo Habkost, 2016/10/17
- [Qemu-devel] [PULL 15/21] intel_iommu: add OnOffAuto intr_eim as "eim" property, Eduardo Habkost, 2016/10/17
- [Qemu-devel] [PULL 16/21] intel_iommu: reject broken EIM, Eduardo Habkost, 2016/10/17
- [Qemu-devel] [PULL 18/21] target-i386: Unset cannot_destroy_with_object_finalize_yet, Eduardo Habkost, 2016/10/17
- [Qemu-devel] [PULL 19/21] target-i386: x86_cpu_load_features() function, Eduardo Habkost, 2016/10/17
- [Qemu-devel] [PULL 17/21] target-i386/kvm: cache the return value of kvm_enable_x2apic(), Eduardo Habkost, 2016/10/17
- [Qemu-devel] [PULL 21/21] target-i386: Don't use cpu->migratable when filtering features, Eduardo Habkost, 2016/10/17
- [Qemu-devel] [PULL 20/21] target-i386: Return runnability information on query-cpu-definitions, Eduardo Habkost, 2016/10/17
- Re: [Qemu-devel] [PULL 00/21] x86 queue, 2016-10-17, Peter Maydell, 2016/10/18