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[Qemu-devel] [PULL 19/25] target-arm: Code changes to implement overwrit
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 19/25] target-arm: Code changes to implement overwrite of tag field on PC load |
Date: |
Mon, 17 Oct 2016 19:40:38 +0100 |
From: Thomas Hanson <address@hidden>
For BR, BLR and RET instructions, if tagged addresses are enabled, the
tag field in the address must be cleared out prior to loading the
address into the PC. Depending on the current EL, it will be set to
either all 0's or all 1's.
Signed-off-by: Thomas Hanson <address@hidden>
Message-id: address@hidden
[PMM: remove unnecessary gen_a64_set_pc_reg() wrapper,
rename gen_a64_set_pc_var() to gen_a64_set_pc(), fix stray
misindentation]
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/translate-a64.c | 82 +++++++++++++++++++++++++++++++++++++++++++---
1 file changed, 77 insertions(+), 5 deletions(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 3b15d2c..16716a2 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -41,6 +41,7 @@ static TCGv_i64 cpu_pc;
/* Load/store exclusive handling */
static TCGv_i64 cpu_exclusive_high;
+static TCGv_i64 cpu_reg(DisasContext *s, int reg);
static const char *regnames[] = {
"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
@@ -176,6 +177,76 @@ void gen_a64_set_pc_im(uint64_t val)
tcg_gen_movi_i64(cpu_pc, val);
}
+/* Load the PC from a generic TCG variable.
+ *
+ * If address tagging is enabled via the TCR TBI bits, then loading
+ * an address into the PC will clear out any tag in the it:
+ * + for EL2 and EL3 there is only one TBI bit, and if it is set
+ * then the address is zero-extended, clearing bits [63:56]
+ * + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0
+ * and TBI1 controls addressses with bit 55 == 1.
+ * If the appropriate TBI bit is set for the address then
+ * the address is sign-extended from bit 55 into bits [63:56]
+ *
+ * We can avoid doing this for relative-branches, because the
+ * PC + offset can never overflow into the tag bits (assuming
+ * that virtual addresses are less than 56 bits wide, as they
+ * are currently), but we must handle it for branch-to-register.
+ */
+static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src)
+{
+
+ if (s->current_el <= 1) {
+ /* Test if NEITHER or BOTH TBI values are set. If so, no need to
+ * examine bit 55 of address, can just generate code.
+ * If mixed, then test via generated code
+ */
+ if (s->tbi0 && s->tbi1) {
+ TCGv_i64 tmp_reg = tcg_temp_new_i64();
+ /* Both bits set, sign extension from bit 55 into [63:56] will
+ * cover both cases
+ */
+ tcg_gen_shli_i64(tmp_reg, src, 8);
+ tcg_gen_sari_i64(cpu_pc, tmp_reg, 8);
+ tcg_temp_free_i64(tmp_reg);
+ } else if (!s->tbi0 && !s->tbi1) {
+ /* Neither bit set, just load it as-is */
+ tcg_gen_mov_i64(cpu_pc, src);
+ } else {
+ TCGv_i64 tcg_tmpval = tcg_temp_new_i64();
+ TCGv_i64 tcg_bit55 = tcg_temp_new_i64();
+ TCGv_i64 tcg_zero = tcg_const_i64(0);
+
+ tcg_gen_andi_i64(tcg_bit55, src, (1ull << 55));
+
+ if (s->tbi0) {
+ /* tbi0==1, tbi1==0, so 0-fill upper byte if bit 55 = 0 */
+ tcg_gen_andi_i64(tcg_tmpval, src,
+ 0x00FFFFFFFFFFFFFFull);
+ tcg_gen_movcond_i64(TCG_COND_EQ, cpu_pc, tcg_bit55, tcg_zero,
+ tcg_tmpval, src);
+ } else {
+ /* tbi0==0, tbi1==1, so 1-fill upper byte if bit 55 = 1 */
+ tcg_gen_ori_i64(tcg_tmpval, src,
+ 0xFF00000000000000ull);
+ tcg_gen_movcond_i64(TCG_COND_NE, cpu_pc, tcg_bit55, tcg_zero,
+ tcg_tmpval, src);
+ }
+ tcg_temp_free_i64(tcg_zero);
+ tcg_temp_free_i64(tcg_bit55);
+ tcg_temp_free_i64(tcg_tmpval);
+ }
+ } else { /* EL > 1 */
+ if (s->tbi0) {
+ /* Force tag byte to all zero */
+ tcg_gen_andi_i64(cpu_pc, src, 0x00FFFFFFFFFFFFFFull);
+ } else {
+ /* Load unmodified address */
+ tcg_gen_mov_i64(cpu_pc, src);
+ }
+ }
+}
+
typedef struct DisasCompare64 {
TCGCond cond;
TCGv_i64 value;
@@ -1704,12 +1775,13 @@ static void disas_uncond_b_reg(DisasContext *s,
uint32_t insn)
switch (opc) {
case 0: /* BR */
- case 2: /* RET */
- tcg_gen_mov_i64(cpu_pc, cpu_reg(s, rn));
- break;
case 1: /* BLR */
- tcg_gen_mov_i64(cpu_pc, cpu_reg(s, rn));
- tcg_gen_movi_i64(cpu_reg(s, 30), s->pc);
+ case 2: /* RET */
+ gen_a64_set_pc(s, cpu_reg(s, rn));
+ /* BLR also needs to load return address */
+ if (opc == 1) {
+ tcg_gen_movi_i64(cpu_reg(s, 30), s->pc);
+ }
break;
case 4: /* ERET */
if (s->current_el == 0) {
--
2.7.4
- [Qemu-devel] [PULL 10/25] hw/arm/boot: allow using a command line specified dtb without a kernel, (continued)
- [Qemu-devel] [PULL 10/25] hw/arm/boot: allow using a command line specified dtb without a kernel, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 08/25] aspeed: create mapping regions for the maximum number of slaves, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 20/25] target-arm: Comments added to identify cases in a switch, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 05/25] aspeed: move the flash module mapping address under the controller definition, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 04/25] aspeed: rename the smc object to fmc, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 24/25] hw/intc/arm_gicv3: Fix ICC register tracepoints, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 02/25] Reducing stack frame size in stream_process_mem2s(), Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 14/25] hw/arm/virt: no ITS on older machine types, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 15/25] tests: add a m25p80 test, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 21/25] Fix masking of PC lower bits when doing exception returns, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 19/25] target-arm: Code changes to implement overwrite of tag field on PC load,
Peter Maydell <=
- [Qemu-devel] [PULL 01/25] docs/generic-loader: Update the document, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 11/25] hw/dma/pl080: Fix bad bit mask (PL080_CONF_M1 | PL080_CONF_M1), Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 17/25] pxa2xx: Auto-assign name for i2c bus in i2c_init_bus., Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 16/25] tests: cleanup ptimer-test, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 03/25] target-arm: kvm: use AddressSpace-specific listener, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 09/25] aspeed: add support for the SMC segment registers, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 18/25] target-arm: Infrastucture changes to enable handling of tagged address loading into PC, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 07/25] aspeed: add support for the AST2500 SoC SMC controllers, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 23/25] target-arm: Add trace events for the generic timers, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 25/25] hw/char/pl011: Add trace events, Peter Maydell, 2016/10/17