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[Qemu-devel] [PULL 22/25] target-arm: Implement dummy MDCCINT_EL1
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 22/25] target-arm: Implement dummy MDCCINT_EL1 |
Date: |
Mon, 17 Oct 2016 19:40:41 +0100 |
MDCCINT_EL1 is part of the DCC debugger communication
channel between the CPU and an attached external debugger.
QEMU doesn't implement this, but since Linux may try
to access this register we need to provide at least
a dummy implementation.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
---
target-arm/helper.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 70e2742..a65f4f2 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -4060,6 +4060,14 @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
.cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
.access = PL1_RW, .accessfn = access_tda,
.type = ARM_CP_NOP },
+ /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications
+ * Channel but Linux may try to access this register. The 32-bit
+ * alias is DBGDCCINT.
+ */
+ { .name = "MDCCINT_EL1", .state = ARM_CP_STATE_BOTH,
+ .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
+ .access = PL1_RW, .accessfn = access_tda,
+ .type = ARM_CP_NOP },
REGINFO_SENTINEL
};
--
2.7.4
- [Qemu-devel] [PULL 11/25] hw/dma/pl080: Fix bad bit mask (PL080_CONF_M1 | PL080_CONF_M1), (continued)
- [Qemu-devel] [PULL 11/25] hw/dma/pl080: Fix bad bit mask (PL080_CONF_M1 | PL080_CONF_M1), Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 17/25] pxa2xx: Auto-assign name for i2c bus in i2c_init_bus., Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 16/25] tests: cleanup ptimer-test, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 03/25] target-arm: kvm: use AddressSpace-specific listener, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 09/25] aspeed: add support for the SMC segment registers, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 18/25] target-arm: Infrastucture changes to enable handling of tagged address loading into PC, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 07/25] aspeed: add support for the AST2500 SoC SMC controllers, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 23/25] target-arm: Add trace events for the generic timers, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 25/25] hw/char/pl011: Add trace events, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 06/25] aspeed: extend the number of host SPI controllers, Peter Maydell, 2016/10/17
- [Qemu-devel] [PULL 22/25] target-arm: Implement dummy MDCCINT_EL1,
Peter Maydell <=
- Re: [Qemu-devel] [PULL 00/25] target-arm queue, Peter Maydell, 2016/10/18